at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 16

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

7. Processor and Architecture
7.1
7.2
7.3
16
ARM7TDMI Processor
Debug and Test Features
Bus Matrix
AT91CAP7E
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• 6 Layers Matrix, handling requests from 6 masters
• Programmable Arbitration strategy
• Burst Management
• One Address Decoder provided per Master
• Boot Mode Select
• Remap Command
RISC Processor Based on ARMv4T Von Neumann Architecture
Two instruction sets
Three-stage pipeline architecture
Integrated embedded in-circuit emulator
Debug Unit
IEEE1149.1 JTAG Boundary-scan on all digital pins
– Runs at up to 80 MHz, providing up to 72 MIPS
– ARM high-performance 32-bit Instruction Set
– Thumb high code density 16-bit Instruction Set
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Two watchpoint units
– Test access port accessible through a JTAG protocol
– Debug communication channel
– Two-pin UART
– Debug communication channel interrupt handling
– Chip ID Register
– Fixed-priority Arbitration
– Round-Robin Arbitration, either with no default master, last accessed default master
– Breaking with Slot Cycle Limit Support
– Undefined Burst Length Support
– Three different slaves may be assigned to each decoded memory area: one for
– Non-volatile Boot Memory can be internal or external
– Selection is made by BMS pin sampled at reset
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
– Allows Handling of Dynamic Exception Vectors
or fixed default master
internal boot, one for external boot, one after remap
8549A–CAP–10/08