at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 26

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

Figure 9-3.
9.6
26
Power Management Controller
AT91CAP7E
Clock Generator Block Diagram
• The Power Management Controller provides the following clocks as shown in Figure 7 below:
• Five flexible operating modes:
– Integrates an input divider to increase output accuracy
– the Processor Clock PCK
– the Master Clock MCK, in particular to the Matrix and the memory interfaces
– the USB Device Clock UDPCK
– independent peripheral clocks (periph_clk), typically at the frequency of MCK
– four programmable clock outputs: PCK0 to PCK3
– Normal Mode, processor and peripherals running at a programmable frequency
– Idle Mode, processor stopped waiting for an interrupt
– Slow Clock Mode, processor and peripherals running at low frequency
– Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency,
– Backup Mode, Main Power Supplies off, VDDBU powered by a battery
processor stopped waiting for an interrupt
XOUT32
PLLRCA
XIN32
XOUT
XIN
Clock Generator
Management
Slow Clock
Oscillators
RC & XTAL
Controller
Oscillator
PLL and
Divider A
PLL and
Divider B
Status
Power
Main
LPF
Control
Slow Clock
SLCK
Main Clock
MAINCK
PLLA Clock
PLLACK
PLLB Clock
PLLBCK
8549A–CAP–10/08