at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 385

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at91cap7e

Manufacturer Part Number
at91cap7e
Description
Customizable Microcontroller
Manufacturer
ATMEL Corporation
Datasheet

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• DSRIC: Data Set Ready Input Change Enable
• DCDIC: Data Carrier Detect Input Change Interrupt Enable
• CTSIC: Clear to Send Input Change Interrupt Enable
• MANE: Manchester Error Interrupt Enable
0: No effect.
1: Enables the corresponding interrupt.
29.7.4
Name:
Access Type:
• RXRDY: RXRDY Interrupt Disable
• TXRDY: TXRDY Interrupt Disable
• RXBRK: Receiver Break Interrupt Disable
• ENDRX: End of Receive Transfer Interrupt Disable
• ENDTX: End of Transmit Interrupt Disable
• OVRE: Overrun Error Interrupt Disable
• FRAME: Framing Error Interrupt Disable
• PARE: Parity Error Interrupt Disable
• TIMEOUT: Time-out Interrupt Disable
• TXEMPTY: TXEMPTY Interrupt Disable
• ITERATION: Iteration Interrupt Disable
• TXBUFE: Buffer Empty Interrupt Disable
8549A–CAP–10/08
PARE
31
23
15
7
USART Interrupt Disable Register
FRAME
30
22
14
6
NACK
OVRE
29
21
13
5
US_IDR
Write-only
RXBUFF
ENDTX
MANE
28
20
12
4
TXBUFE
ENDRX
CTSIC
27
19
11
3
ITERATION
RXBRK
DCDIC
26
18
10
2
TXEMPTY
TXRDY
DSRIC
25
17
9
1
AT91CAP7E
TIMEOUT
RXRDY
RIIC
24
16
8
0
385

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