at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 470

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

32.5.4
Figure 32-2. EOCx and DRDY Flag Behavior
470
(ADC_CHSR)
(ADC_SR)
(ADC_SR)
EOCx
DRDY
CHx
AT91CAP7E
Conversion Results
Write the ADC_CR
with START = 1
When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data
Register (ADC_CDR) of the current channel and in the ADC Last Converted Data Register
(ADC_LCDR).
The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of
a connected PDC channel, DRDY rising triggers a data transfer request. In any case, either
EOC and DRDY can trigger an interrupt.
Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading ADC_LCDR
clears the DRDY bit and the EOC bit corresponding to the last converted channel.
If the ADC_CDR is not read before further incoming data is converted, the corresponding Over-
run Error (OVRE) flag is set in the Status Register (ADC_SR).
In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun
Error) in ADC_SR.
The OVRE and GOVRE flags are automatically cleared when ADC_SR is read.
Conversion Time
Read the ADC_CDRx
Write the ADC_CR
with START = 1
Conversion Time
Read the ADC_LCDR
8549A–CAP–10/08