p87lpc778 NXP Semiconductors, p87lpc778 Datasheet - Page 14

• Manufacturer Part Number: p87lpc778
• Description: Cmos Single-chip 8-bit 80c51 Microcontroller 128-byte Data Ram, 8 Kb Otp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12378
Product data
8.4 A/D timing
Table 6:
Table 7:
The A/D may be clocked in one of two ways. The default is to use the CPU clock as
the A/D clock source. When used in this manner, the A/D completes a conversion in
31 machine cycles. The A/D may be operated up to the maximum CPU clock rate of
20 MHz, giving a conversion time of 9.3 s. The formula for calculating A/D
conversion time when the CPU clock runs the A/D is: 186 s / CPU clock rate
(in MHz). To obtain accurate A/D conversion results, the CPU clock must be at least
1 MHz.
The A/D may also be clocked by the on-chip RC oscillator, even if the RC oscillator is
not used as the CPU clock. This is accomplished by setting the RCCLK bit in
ADCON. This arrangement has several advantages. First, the A/D conversion time is
faster at lower CPU clock rates. Also, the CPU may be run at speeds below 1 MHz
without affecting A/D accuracy. Finally, the Power-down mode may be used to
completely shut down the CPU and its oscillator, along with other peripheral
functions, in order to obtain the best possible A/D accuracy.
When the A/D is operated from the RCCLK while the CPU is running from another
clock source, 3 or 4 machine cycles are used to synchronize A/D operation. The time
can range from a minimum of 3 machine cycles (at the CPU clock rate) + 108 RC
clocks to a maximum of 4 machine cycles (at the CPU clock rate) + 112 RC clocks.
Example A/D conversion times at various CPU clock rates are shown in
the table, maximum times for RCCLK = 1 use an RC clock frequency of 6 MHz.
Minimum times for RCCLK = 1 use an RC clock frequency of. Nominal time assume
an ideal RC clock frequency of 6 MHz and an average of 3.5 machine cycles at the
CPU clock rate.
ADCI, ADCS
0 0
0 1
1 0
1 1
AADR1, AADR0
0 0
0 1
1 0
1 1
ADCON - ADCI, ADCS A/D status
ADCON - AADR1, AADR0 A/D input selection
A/D status
A/D not busy, a conversion can be started
A/D busy, the start of a new conversion is blocked.
An A/D conversion is complete. ADCI must be cleared prior to starting a
new conversion.
An A/D conversion is complete. ADCI must be cleared prior to starting a
new conversion. This state exists for one machine cycle as an A/D
conversion is completed.
Rev. 01 — 31 March 2004
A/D input selected
AD0 (P0.3)
AD1 (P0.4)
AD2 (P0.5)
AD3 (P0.6)
CMOS single-chip 8-bit microcontroller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P87LPC778
Table
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