p87lpc778 NXP Semiconductors, p87lpc778 Datasheet - Page 41

• Manufacturer Part Number: p87lpc778
• Description: Cmos Single-chip 8-bit 80c51 Microcontroller 128-byte Data Ram, 8 Kb Otp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12378
Product data
Fig 16. Block diagram of oscillator control
FOSC2 (UCFG1.2)
FOSC1 (UCFG1.1)
FOSC0 (UCFG1.0)
crystal: medium
power monitor reset
crystal: high
internal RC
crystal: low
clock input
frequency
frequency
frequency
oscillator
external
power down
8.10.7 CPU clock modification: CLKR and DIVM
For backward compatibility, the CLKR configuration bit allows setting the P87LPC778
instruction and peripheral timing to match standard 80C51 timing by dividing the CPU
clock by two. Default timing for the P87LPC778 is 6 CPU clocks per machine cycle
while standard 80C51 timing is 12 clocks per machine cycle. This division also
applies to peripheral timing, allowing 80C51 code that is oscillator frequency and/or
timer rate dependent. The CLKR bit is located in the EPROM configuration register
UCFG1, described under
Fig 15. Using an external clock input.
The oscillator must be configured in the External Clock input mode. A clock output may be
obtained on the X2 pin by setting the ENCLK bit in the P2M1 register.
CLOCK SELECT
SOURCES
CLOCK
SELECT
CLOCK
OUT
XTAL
Rev. 01 — 31 March 2004
external oscillator signal
CMOS compatible
Section 8.18 “EPROM characteristics” on page
RESET
COUNT
10-BIT RIPPLE COUNTER
(UCFG1.3)
oscillator startup timer
CLKR
CMOS single-chip 8-bit microcontroller
COUNT 1024
COUNT 256
(DIVM REGISTER) AND
X1
X2
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
CLKR SELECT
87LPC778
DIVIDE-BY-M
002aaa633
1 / 2
P87LPC778
CPU
clock
66.
002aaa634
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