p87lpc778 NXP Semiconductors, p87lpc778 Datasheet - Page 31

• Manufacturer Part Number: p87lpc778
• Description: Cmos Single-chip 8-bit 80c51 Microcontroller 128-byte Data Ram, 8 Kb Otp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12378
Product data
Table 27:
Not bit addressable; Reset value: 00H
Table 28:
Values to be used in the CT1 and CT0 bits are shown in
I
actual oscillator rate to the f
found in the first line of the table where CPU clock max is greater than or equal to the
actual frequency.
CT1/CT0. This allows calculation of the actual minimum high and low times for SCL
as follows:
For instance, at an 8 MHz frequency, with CT1/CT0 set to 1 0, the minimum SCL high
and low times will be 5.25 s.
in machine cycles) for each CT1/CT0 combination. The timeout period varies
because of the way in which minimum SCL high and low times are measured. When
the I
value dependent upon CT1/CT0. The pre-load value is chosen such that a minimum
SCL high or low time has elapsed when Timer I reaches a count of 008 (the actual
value pre-loaded into Timer I is 8 minus the machine cycle count).
SCL min high/low time (in microseconds)
Bit
7
6
5
4
3, 2
1, 0
2
Bit
Symbol SLAVEN
C-bus to run at the maximum rate for a particular oscillator frequency, compare the
2
C-bus interface is operating, Timer I is pre-loaded at every SCL transition with a
I2CFG - I
I2CFG - I
Symbol
SLAVEN
MASTRQ
CLRTI
TIRUN
-
CT1, CT0
7
Table 30
Rev. 01 — 31 March 2004
2
2
C-bus configuration register (address C8h) bit allocation
C-bus configuration register (address C8h) bit description
MASTRQ
Description
Slave Enable. Writing a ‘1’ this bit enables the slave functions of
the I
I
by an I
Master Request. Writing a ‘1’ to this bit requests mastership of the
I
from ‘0’ to ‘1’, action is delayed until a stop condition is detected. A
start condition is sent and DRDY is set (thus making ATN = 1 and
generating an I
mastership status of the I
MASTRQ is cleared by an I
Writing a ‘1’ to this bit clears the Timer I overflow flag. This bit
position always reads as a ‘0’.
Writing a ‘1’ to this bit lets Timer I run; a ‘0’ stops and clears it.
Together with SLAVEN, MASTRQ, and MASTER, this bit
determines operational modes as shown in
Reserved for future use. Should not be set to ‘1’ by user programs.
These two bits are programmed as a function of the CPU clock
rate, to optimize the MIN HI and LO time of SCL when this device
is a master on the I
bits controls both of these parameters, and also the timing for stop
and start conditions.
6
2
2
C-bus hardware is disabled. This bit is cleared to ‘0’ by reset and
C-bus. If a transmission is in progress when this bit is changed
also shows the machine cycle count for various settings of
osc
2
C-bus subsystem. If SLAVEN and MASTRQ are ‘0’, the
Table 30
2
max column in the table. The value for CT1 and CT0 is
C-bus time-out.
CLRTI
5
2
C-bus interrupt). When a master wishes to release
also shows the Timer I timeout period (given
=
TIRUN
2
----------------------------------------------- -
CPUclock (in MHz)
C-bus. The time value determined by these
6 * min time count
CMOS single-chip 8-bit microcontroller
4
2
C-bus, it writes a ‘1’ to XSTP in I2CON.
2
C-bus time-out.
3
-
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table
P87LPC778
2
-
30. To allow the
Table
CT1
29.
1
CT0
31 of 79
0
(5)