p87lpc778 NXP Semiconductors, p87lpc778 Datasheet - Page 44

• Manufacturer Part Number: p87lpc778
• Description: Cmos Single-chip 8-bit 80c51 Microcontroller 128-byte Data Ram, 8 Kb Otp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12378
Product data
8.12.3 Low voltage EPROM operation
Table 40:
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during Power-down. These include the Brownout
Detect, Watchdog Timer, and Comparators.
The EPROM array contains some analog circuits that are not required when V
less than 4 V, but are required for a V
when set by software, will Power-down these analog circuits resulting in a reduced
supply current. LPEP is cleared only by Power-on reset, so it may be set ONLY for
applications that always operate with V
Table 41:
Not bit addressable; Reset value: 30H for a Power-on reset; 20H for a Brownout reset; 00H for
other reset sources.
Table 42:
Wake-up Source
External Interrupt 0 or 1
Keyboard Interrupt
Comparator 1 or 2
Watchdog Timer Reset
Watchdog Timer Interrupt
Brownout Detect Reset
Brownout Detect Interrupt
Reset Input
A/D Converter
Bit
7
6
5
Bit
Symbol SMOD1
Symbol
SMOD1
SMOD0
BOF
Interrupt sources
PCON - Power control register (address 87H) bit allocation
PCON - Power control register (address 87H) bit description
7
Rev. 01 — 31 March 2004
SMOD0
6
Description
When set, this bit doubles the UART baud rate for modes 1, 2, and
3.
This bit selects the function of bit 7 of the SCON SFR. When 0,
SCON.7 is the SM0 bit. When 1, SCON.7 is the FE (Framing Error)
flag. See Tables
Brown Out Flag. Set automatically when a brownout reset or
interrupt has occurred. Also set at Power-on. Cleared by software.
Refer to
additional information.
Conditions
The corresponding interrupt must be enabled.
The keyboard interrupt feature must be enabled and properly
set up. The corresponding interrupt must be enabled.
The comparator(s) must be enabled and properly set up. The
corresponding interrupt must be enabled.
The Watchdog timer must be enabled via the WDTE bit in the
UCFG1 EPROM configuration byte.
The WDTE bit in the UCFG1 EPROM configuration byte must
not be set. The corresponding interrupt must be enabled.
The BOD bit in AUXR1 must not be set (brownout detect not
disabled). The BOI bit in AUXR1 must not be set (brownout
interrupt disabled).
The BOD bit in AUXR1 must not be set (brownout detect not
disabled). The BOI bit in AUXR1 must be set (brownout interrupt
enabled). The corresponding interrupt must be enabled.
The external reset input must be enabled.
Must use internal RC clock (RCCLK = 1) for A/D converter to
work in Power-down mode. The A/D must be enabled and
properly set up. The corresponding interrupt must be enabled.
BOF
Section 8.11 “Power monitoring functions” on page 42
5
DD
DD
48
POF
greater than 4 V. The LPEP bit (AUXR.4),
4
less than 4 V.
and
CMOS single-chip 8-bit microcontroller
49
for additional information.
GF1
3
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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P87LPC778
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