p87lpc778 NXP Semiconductors, p87lpc778 Datasheet - Page 48

• Manufacturer Part Number: p87lpc778
• Description: Cmos Single-chip 8-bit 80c51 Microcontroller 128-byte Data Ram, 8 Kb Otp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12378
Product data
8.14.2 Mode 1
8.14.3 Mode 2
8.14.4 Mode 3
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and
TLn) are used. See
Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload,
as shown in
with the contents of THn, which must be preset by software. The reload leaves THn
unchanged. Mode 2 operation is the same for Timer0 and Timer1.
When Timer1 is in Mode 3 it is stopped. The effect is the same as setting TR1 = 0.
Timer0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic
for Mode 3 on Timer0 is shown in
GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine
cycles) and takes over the use of TR1 and TF1 from Timer1. Thus, TH0 now controls
the ‘Timer1’ interrupt.
Mode 3 is provided for applications that require an extra 8-bit timer. With Timer0 in
Mode 3, an P87LPC778 can look like it has three Timer/Counters. When Timer0 is in
Mode 3, Timer1 can be turned on and off by switching it into and out of its own Mode
3. It can still be used by the serial port as a baud rate generator, or in any application
not requiring an interrupt.
Table 46:
Bit addressable; Reset value: 00H
Table 47:
Bit
7
6
5
4
3
Bit
Symbol
Symbol
TF1
TR1
TF0
TR0
IE1
TCON - Timer/counter control register (address 88H) bit allocation
TCON - Timer/counter control register (address 88H) bit description
TF1
Figure
7
Rev. 01 — 31 March 2004
21. Overflow from TLn not only sets TFn, but also reloads TLn
Figure
TR1
6
Description
Timer1 overflow flag. Set by hardware on Timer/Counter overflow.
Cleared by hardware when the interrupt is processed, or by
software.
Timer1 Run control bit. Set/cleared by software to turn
Timer/Counter 1 on/off.
Timer0 overflow flag. Set by hardware on Timer/Counter overflow.
Cleared by hardware when the processor vectors to the interrupt
routine, or by software.
Timer0 Run control bit. Set/cleared by software to turn
Timer/Counter 0 on/off.
Interrupt 1 Edge flag. Set by hardware when external interrupt 1
edge is detected. Cleared by hardware when the interrupt is
processed, or by software.
20.
TF0
5
Figure
TR0
22. TL0 uses the Timer0 control bits: C/T,
4
CMOS single-chip 8-bit microcontroller
IE1
3
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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