p87lpc778 NXP Semiconductors, p87lpc778 Datasheet - Page 28

• Manufacturer Part Number: p87lpc778
• Description: Cmos Single-chip 8-bit 80c51 Microcontroller 128-byte Data Ram, 8 Kb Otp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12378
Product data
8.7.2 Reading I2CON
8.7.3 Checking ATN and DRDY
Table 24:
RDAT — The data from SDA is captured into ‘Receive DATa’ whenever a rising edge
occurs on SCL. RDAT is also available (with seven low-order zeros) in the I2DAT
register. The difference between reading it here and there is that reading I2DAT
clears DRDY, allowing the I
seven bits of a received byte are read from I2DAT, while the 8th is read here. Then
I2DAT can be written to send the Acknowledge bit and clear DRDY.
ATN — ‘ATteNtion’ is ‘1’ when one or more of DRDY, ARL, STR, or STP is ‘1’. Thus,
ATN comprises a single bit that can be tested to release the I
from a ‘wait loop.’
DRDY — ‘Data ReaDY’ (and thus ATN) is set when a rising edge occurs on SCL,
except at idle slave. DRDY is cleared by writing CDR = 1, or by writing or reading the
I2DAT register. The following low period on SCL is stretched until the program
responds by clearing DRDY.
When a program detects ATN = 1, it should next check DRDY. If DRDY = 1, then if it
receives the last bit, it should capture the data from RDAT (in I2DAT or I2CON). Next,
if the next bit is to be sent, it should be written to I2DAT. One way or another, it should
clear DRDY and then return to monitoring ATN. Note that if any of ARL, STR, or STP
is set, clearing DRDY will not release SCL to HIGH, so that the I
to the next bit. If a program detects ATN = 1, and DRDY = 0, it should go on to
examine ARL, STR, and STP.
Bit Symbol
7
6
5
4
3
2
1
0
RDAT
CXA
ATN
IDLE
DRDY
CDR
ARL
CARL
STR
CSTR
STP
CSTP
MASTER R
XSTR
-
XSTP
I2CON - I
Access Description
R
W
R
W
R
W
R
W
R
W
R
W
W
R
W
Rev. 01 — 31 March 2004
2
C-bus control register (address D8H) bit description
The most recently received data bit
Clears the transmit active flag
ATN = 1 if any of the flags DRDY, ARL, STP, or STP = 1
In the I
hardware to ignore the bus until it is needed again
Data Ready flag, set when there is a rising edge on SCL
Writing a ‘1’ to this bit clears the DRDY flag
Arbitration Loss flag, set when arbitration is lost while in the transmit
mode
Writing a ‘1’ to this bit clears the CARL flag
Start flag, set when a start condition is detected at a master or
non-idle slave
Writing a ‘1’ to this bit clears the STR flag
Stop flag, set when a stop condition is detected at a master or
non-idle slave
Writing a ‘1’ to this bit clears the STP flag
Indicates whether this device is currently as bus master
Writing a ‘1’ to this bit causes a repeated start condition to be
generated
Undefined
Writing a ‘1’ to this bit causes a stop condition to be generated
2
C-bus to proceed on to another bit. Typically, the first
2
C-bus slave mode, writing a ‘1’ to this bit causes the I
CMOS single-chip 8-bit microcontroller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P87LPC778
2
C-bus service routine
2
C-bus will not go on
2
C-bus
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