mc9s08qg8 Freescale Semiconductor, Inc, mc9s08qg8 Datasheet - Page 217

• Manufacturer Part Number: mc9s08qg8
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

15.3
The SPI has five 8-bit registers to select SPI options, control baud rate, report SPI status, and for
transmit/receive data.
Refer to the direct-page register summary in the
assignments for all SPI registers. This section refers to registers and control bits only by their names, and
a Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
15.3.1
This read/write register includes the SPI enable control, interrupt enables, and configuration options.
Freescale Semiconductor
Reset
SPTIE
MSTR
CPHA
CPOL
Field
SPIE
SPE
7
6
5
4
3
2
W
R
Register Definition
SPIE
SPI Control Register 1 (SPIC1)
SPI Interrupt Enable (for SPRF and MODF) — This is the interrupt enable for SPI receive buffer full (SPRF)
and mode fault (MODF) events.
0 Interrupts from SPRF and MODF inhibited (use polling)
1 When SPRF or MODF is 1, request a hardware interrupt
SPI System Enable — Disabling the SPI halts any transfer that is in progress, clears data buffers, and initializes
internal state machines. SPRF is cleared and SPTEF is set to indicate the SPI transmit data buffer is empty.
0 SPI system inactive
1 SPI system enabled
SPI Transmit Interrupt Enable — This is the interrupt enable bit for SPI transmit buffer empty (SPTEF).
0 Interrupts from SPTEF inhibited (use polling)
1 When SPTEF is 1, hardware interrupt requested
Master/Slave Mode Select
0 SPI module configured as a slave SPI device
1 SPI module configured as a master SPI device
Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a
slave SPI device. Refer to
0 Active-high SPI clock (idles low)
1 Active-low SPI clock (idles high)
Clock Phase — This bit selects one of two clock formats for different kinds of synchronous serial peripheral
devices. Refer to
0 First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer
1 First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer
0
7
SPE
0
6
Section 15.4.1, “SPI Clock
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Figure 15-5. SPI Control Register 1 (SPIC1)
Section 15.4.1, “SPI Clock
Table 15-1. SPIC1 Field Descriptions
SPTIE
0
5
Memory
MSTR
Formats”
0
4
Description
chapter of this data sheet for the absolute address
Formats”
for more details.
CPOL
3
0
for more details.
CPHA
1
2
Serial Peripheral Interface (S08SPIV3)
SSOE
0
1
LSBFE
0
0
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