mc9s08qg8 Freescale Semiconductor, Inc, mc9s08qg8 Datasheet - Page 232

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mc9s08qg8

Manufacturer Part Number
mc9s08qg8
Description
Hcs08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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0
Timer/PWM (S08TPMV2)
16.3.2
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPMCNTH or TPMCNTL) latches the contents of both bytes into a buffer where they
remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The coherency
mechanism is automatically restarted by an MCU reset, a write of any value to TPMCNTH or TPMCNTL,
or any write to the timer status/control register (TPMSC).
Reset clears the TPM counter registers.
232
Reset
W
R
Bit 15
Timer Counter Registers (TPMCNTH:TPMCNTL)
1
2
0
7
The maximum frequency that is allowed as an external clock is one-fourth of the bus
frequency.
If the external clock input is shared with channel n and is selected as the TPM clock source,
the corresponding ELSnB:ELSnA control bits should be set to 0:0 so channel n does not try
to use the same pin for a conflicting function.
CLKSB:CLKSA
PS2:PS1:PS0
0:0
0:1
1:0
1:1
14
0
6
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
Figure 16-4. Timer Counter Register High (TPMCNTH)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Table 16-2. TPM Clock Source Selection
Table 16-3. Prescale Divisor Selection
Any write to TPMCNTH clears the 16-bit counter.
13
0
5
TPM Clock Source to Prescaler Input
12
No clock selected (TPM disabled)
0
4
External source (TPMCLK)
Fixed system clock (XCLK)
Bus rate clock (BUSCLK)
TPM Clock Source Divided-By
11
3
0
128
16
32
64
1
2
4
8
10
1,2
0
2
Freescale Semiconductor
9
0
1
Bit 8
0
0

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