mc9s08qg8 Freescale Semiconductor, Inc, mc9s08qg8 Datasheet - Page 219

• Manufacturer Part Number: mc9s08qg8
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

15.3.3
This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or
written at any time.
Freescale Semiconductor
SPPR[2:0]
SPISWAI
SPR[2:0]
Reset
SPC0
Field
Field
6:4
2:0
1
0
W
R
SPI Baud Rate Register (SPIBR)
SPI Stop in Wait Mode
0 SPI clocks continue to operate in wait mode
1 SPI clocks stop when the MCU enters wait mode
SPI Pin Control 0 — The SPC0 bit chooses single-wire bidirectional mode. If MSTR = 0 (slave mode), the SPI
uses the MISO (SISO) pin for bidirectional SPI data transfers. If MSTR = 1 (master mode), the SPI uses the
MOSI (MOMI) pin for bidirectional SPI data transfers. When SPC0 = 1, BIDIROE is used to enable or disable the
output driver for the single bidirectional SPI I/O pin.
0 SPI uses separate pins for data input and data output
1 SPI configured for single-wire bidirectional operation
SPI Baud Rate Prescale Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate prescaler
as shown in
drives the input of the SPI baud rate divider (see
SPI Baud Rate Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in
Table
divider is the SPI bit rate clock for master mode.
0
0
7
15-6. The input to this divider comes from the SPI baud rate prescaler (see
= Unimplemented or Reserved
Table
SPPR2
Table 15-3. SPIC2 Register Field Descriptions (continued)
0
6
SPPR2:SPPR1:SPPR0
15-5. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Table 15-4. SPIBR Register Field Descriptions
Figure 15-7. SPI Baud Rate Register (SPIBR)
Table 15-5. SPI Baud Rate Prescaler Divisor
SPPR1
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
0
5
SPPR0
0
4
Figure
Description
Description
15-4).
Prescaler Divisor
3
0
0
1
2
3
4
5
6
7
8
SPR2
0
2
Serial Peripheral Interface (S08SPIV3)
Figure
15-4). The output of this
SPR1
0
1
SPR0
0
0
219