m52s128324a Elite Semiconductor Memory Technology Inc., m52s128324a Datasheet - Page 13

• Manufacturer Part Number: m52s128324a
• Description: 1m X 32 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
DEVICE OPERATIONS (Continued)
shares part of the internal circuitry to reduce chip area,
therefore
simultaneously. Also the noise generated during sensing of
each bank of SDRAM is high requiring some time for power
supplies to recover before another bank can be sensed
reliably. t
activating different bank. The number of clock cycles required
between different bank activation must be calculated similar to
t
to be active to initiate sensing and restoring the complete row
of dynamic cells is determined by t
activate command must satisfy t
precharge command to that active bank can be asserted. The
maximum time any bank can be in the active state is
determined by t
similar to t
BURST READ
The burst read command is used to access burst of data on
consecutive clock cycles from an active row in an active bank.
The burst read command is issued by asserting low on CS
and RAS with WE being high on the positive edge of the
clock. The bank must be active for at least t
burst read command is issued. The first output appears in CAS
latency number of clock cycles after the issue of burst read
command. The burst length, burst sequence and latency from
the burst read command is determined by the mode register
which is already programmed. The burst read can be initiated
on any column address of the active row. The address wraps
around if the initial address does not start from a boundary
such that number of outputs from each I/O are equal to the
burst length programmed in the mode register. The output
goes into high-impedance at the end of burst, unless a new
burst read was initiated to keep the data output gapless. The
burst read can be terminated by issuing another burst read or
burst write in the same bank or the other active bank or a
precharge command to the same bank. The burst stop
command is valid at every page burst length.
BURST WRITE
The burst write command is similar to burst read command
and is used to write data into the SDRAM on consecutive clock
cycles in adjacent addresses depending on burst length and
burst sequence. By asserting low on CS , CAS and WE
with valid column address, a write burst is initiated. The data
inputs are provided for the initial address in the same clock
cycle as the burst write command. The input buffer is
deselected at the end of the burst length, even though the
internal writing can be completed yet. The writing can be
complete by issuing a burst read and DQM for blocking data
inputs or burst write in the same or another active bank. The
burst stop command is valid at every burst length. The write
burst can also be terminated by using DQM for blocking data
and procreating the bank t
written into the active row. See DQM OPERATION also.
Elite Semiconductor Memory Technology Inc.
RCD (min)
The SDRAM has four internal banks in the same chip and
specification. The minimum time required for the bank
RRD (min)
RCD
it
specification.
restricts
RAS
specifies the minimum time required between
(max) and t
the
RDL
after the last data input to be
activation
RAS (min)
RAS
RAS (min)
(max) can be calculated
specification before a
. Every SDRAM bank
RCD (min)
of
four
before the
banks
The DQM is used mask input and output operations. It
works similar to OE during operation and inhibits writing
during write operation. The read latency is two cycles from
DQM and zero cycle for write, which means DQM masking
occurs two cycles later in read cycle and occurs in the
same cycle during write cycle. DQM operation is
synchronous with the clock. The DQM signal is important
during burst interrupts of write with read or precharge in
the SDRAM. Due to asynchronous nature of the internal
write, the DQM operation is critical to avoid unwanted or
incomplete writes when the complete burst write is
required. Please refer to DQM timing diagram also.
The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the
timing to satisfy t
burst length and CAS latency. The auto precharge
command is issued at the same time as burst write by
asserting high on A10/AP, the bank is precharge command
is asserted. Once auto precharge command is given, no
new commands are possible to that particular bank until
the bank achieves idle state.
ALL BANKS PRECHARGE
Four banks can be precharged at the same time by using
Precharge all command. Asserting low on CS , RAS ,
and WE with high on A10/AP after all banks have
satisfied t
banks. At the end of t
banks are in idle state.
PRECHARGE
AUTO PRECHARGE
DQM OPERATION
The precharge is performed on an active bank by
asserting low on clock cycles required between bank
activate and clock cycles required between bank activate
and CS , RAS , WE and A10/AP with valid BA0~BA1
of the bank to be procharged. The precharge command
can be asserted anytime after t
bank active command in the desired bank. t
as the minimum number of clock cycles required to
complete row precharge is calculated by dividing t
clock cycle time and rounding up to the next higher
integer. Care should be taken to make sure that burst
write is completed or DQM is used to inhibit writing before
precharge command is asserted. The maximum time any
bank can be active is specified by t
each bank activate command. At the end of precharge,
the bank enters the idle state and is ready to be activated
again. Entry to power-down, Auto refresh, Self refresh and
Mode register set etc. is possible only when all banks are
in idle state.
RAS (min)
requirement, performs precharge on all
RAS (min)
RP
Publication Date: Mar. 2009
Revision: 1.4
after performing precharge all, all
and “t
M52S128324A
RAS (min)
RP
” for the programmed
RAS
is satisfy from the
(max). Therefore,
RP
is defined
13/47
RP
with