m52s128324a Elite Semiconductor Memory Technology Inc., m52s128324a Datasheet - Page 17

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m52s128324a

Manufacturer Part Number
m52s128324a
Description
1m X 32 Bit X 4 Banks Synchronous Dram
Manufacturer
Elite Semiconductor Memory Technology Inc.
Datasheet
ESMT
Self refresh entry command
remains low. When CKE goes to high, the M52S128324A exits the self refresh mode.
internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
Burst stop command
This command terminates the current burst operation.
Burst stop is valid at every burst length.
No operation
this command.
Elite Semiconductor Memory Technology Inc.
After the command execution, self refresh operation continues while CKE
During self refresh mode, refresh interval and refresh operation are performed
This command is not a execution command. No operations begin or terminate by
( CS , RAS , CAS , CKE = Low , WE = High)
( CS , WE = Low, RAS , CAS = High)
( CS = Low , RAS , CAS , WE = High)
BA0, BA1
(Bank select)
Publication Date: Mar. 2009
Revision: 1.4
BA0, BA1
(Bank select)
BA0, BA1
(Bank select)
Fig. 8 Burst stop command
RAS
RAS
CKE
M52S128324A
CKE
CAS
RAS
CLK
CKE
CAS
A10
CLK
CAS
CLK
Add
A10
A10
Add
WE
Fig. 7 Self refresh entry
CS
Add
WE
WE
CS
CS
Fig. 9 No operation
command
H
H
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