m52s128324a Elite Semiconductor Memory Technology Inc., m52s128324a Datasheet - Page 43

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m52s128324a

Manufacturer Part Number
m52s128324a
Description
1m X 32 Bit X 4 Banks Synchronous Dram
Manufacturer
Elite Semiconductor Memory Technology Inc.
Datasheet
C L O C K
A D D R
ESMT
Mode Register Set Cycle
All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
*Note : 1. CS , RAS , CAS , & WE activation at the same clock cycle with address key will set internal mode register.
Elite Semiconductor Memory Technology Inc.
C K E
D Q M
C A S
R A S
W E
C S
D Q
MODE REGISTER SET CYCLE
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
0
1
M R S
K e y
* N o t e 2
* N o t e 1
* N o t e 3
2
H I - Z
H I G H
C o m m a n d
3
N e w
R a
4
5
6
Auto Refresh Cycle
0
A u t o R e f r e s h
1
2
H I G H
3
H I - Z
4
Publication Date: Mar. 2009
Revision: 1.4
5
t
R C
M52S128324A
6
7
8
N e w C o m m a n d
9
: D o n ' t C a r e
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1 0

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