ia186es Innovasic Semiconductor Inc., ia186es Datasheet - Page 100

• Manufacturer Part Number: ia186es
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
5.1.44 REQST (02eh) (Master Mode)
Interrupt REQueST Register. This is a read-only register and such a read results in the status of
the interrupt request bits presented to the interrupt controller. The REQST register is undefined
on reset (see Table 65).
Table 65. Interrupt Request Register (Master Mode)
15
14
Note: The TMR bit in the REQST register is a logical OR of these timer
interrupt requests.
Reserved
Bit [15]—DHLT DMA Halt → DMA activity is halted when this bit is 1. It is set to 1
automatically when any non-maskable interrupt occurs and is cleared to 0 when an IRET
instruction is executed. Interrupt handlers and other time critical software may modify
this bit directly to disable DMA transfers. However, the DHLT bit should not be
modified by software if the timer interrupts are enabled as the function of this register as
an interrupt request register for the timers would be compromised.
Bits [14–3]—Reserved.
Bit [2–0]—TMR [2–0] Timer Interrupt Request → A pending interrupt request is
indicated by the respective timer, when any of these bits is 1.
Bits [15–11]—Reserved.
Bit [10]—SP0 Serial Port 0 Interrupt Request → This is the serial port 0 interrupt state
and when enabled is the logical OR of all the serial port 0 interrupt sources, THRE, RDR,
BRK1, BRK0, FER, PER, and OER.
Bit [9]—SP1 Serial Port 1 Interrupt Request → This is the serial port 1 interrupt state and
when enabled is the logical OR of all the serial port 1 interrupt sources, THRE, RDR,
BRK1, BRK0, FER, PER, and OER.
Bits [8–4]—I [4–0] Interrupt Requests → When any of these bits is set to 1, it indicates
that the relevant interrupt has a pending interrupt.
Bit [3]—D1/I6 DMA Channel 1/Interrupt 6 Request → When set to 1, it indicates that
either the DMA channel 1 or int6 has a pending interrupt.
Bit [2]—D0/I5 DMA Channel 0/Interrupt 5 Request → When set to 1, it indicates that
either the DMA channel 0 or int5 has a pending interrupt.
13
12
11
®
SP0
10
SP1
9
I4
8
UNCONTROLLED WHEN PRINTED OR COPIED
I3
7
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I2
6
IA211050902-15
I1
5
IO
4
D1/I6
3
D0/I5
2
Res
1
December 24, 2008
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TMR
0
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