ia186es Innovasic Semiconductor Inc., ia186es Datasheet - Page 108

• Manufacturer Part Number: ia186es
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
6.
Table 77
respectively.
Table 79
the write cycle timing.
Figure 16
Figure 17
Figure 18
timing.
acknowledge cycle timing.
software halt cycle timing.
save mode.
Figure 23
ready.
Figure 26
present the bus hold entering and bus hold leaving, respectively.
bus hold timing.
Table 77. Alphabetic Key to Waveform Parameters
a
In nanoseconds.
No.
49
51
52
87
14
12
66
65
24
45
68
38
44
67
18
22
64
63
tARYCH
tARYCHL ardy Inactive Holding Time
tARYLCL ardy Setup Time
tAVBL
tAVCH
tAVLL
tAVRL
tAVWL
tAZRL
tCH1CH2 clkouta Rise Time
tCHAV
tCHCK
tCHCL
tCHCSV
tCHCSX
tCHCTV
tCHCV
tCHCZ
Figure 25
AC Specifications
Name
Figure 19
and
presents the read cycle timing.
presents the PSRAM read cycle.
presents the PSRAM write cycle.
presents the PSRAM refresh cycle.
presents the srdy—synchronous ready.
and
Table 86
Table 78
Figure 12
Figure 27
ardy Resolution Transition Setup Time
a Address Valid to whb_n/wlb_n Low
ad Address Valid to Clock High
ad Address Valid to ale Low
a Address Valid to rd_n Low
a Address Valid to wr_n Low
ad Address Float to rd_n Active
clkouta High to a Address Valid
x1 High Time
clkouta High Time
clkouta High to lcs_n/usc_n Valid
mcs_n/pcs_n Inactive Delay
Control Active Delay 2
Command Lines Valid Delay (after Float)
Command Lines Float Delay
presents the peripherals.
presents the interrupt acknowledge cycle.
®
presents the clock timing.
present the alphabetic and numeric keys to waveform parameters,
Figure 15
presents the read cycle.
present Reset 1 and Reset 2, respectively.
Figure 21
Figure 20
Description
presents the multiple write cycles.
UNCONTROLLED WHEN PRINTED OR COPIED
presents the active mode.
presents the software halt cycle.
Figure 14
Table 87
Table 81
Table 82
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Table 83
IA211050902-15
Figure 13
Figure 24
presents the write cycle.
presents the ready and peripheral timing.
presents the PSRAM read cycle timing.
presents the PSRAM write cycle timing.
presents the PSRAM refresh cycle
tCLCL+tCHCL
tCLCL+tCHCL
presents the multiple read cycles.
tCHCL-1.5
presents the ardy—asynchronous
tCLCL/2
Table 84
tCHCL
Min
7.5
9
6
9
0
0
0
0
0
0
0
0
0
Figure 22
Table 88
a
Figure 28
presents the interrupt
Table 85
tCHCL
Max
presents the reset and
presents the power-
12
10
12
12
–
–
–
–
–
–
–
–
3
8
–
–
9
Table 80
and
a
December 24, 2008
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presents the
Figure 29
Customer Support:
presents
Data Sheet
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