ia186es Innovasic Semiconductor Inc., ia186es Datasheet - Page 37

• Manufacturer Part Number: ia186es
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
2.2.21 int4/pio30—Maskable Interrupt Request 4 (asynchronous input)
The int4 pin provides an indication that an interrupt request has occurred. And provided that int4
is not masked, program execution will continue at the location specified by the int4 vector in the
interrupt vector table. Although interrupt requests are asynchronous, they are synchronized
internally and may be edge- or level-triggered. To ensure that it is recognized, the assertion of
the interrupt request must be maintained until it is handled. In the case where PWD mode is
selected, int4 indicates a High-to-Low transition of the PWD signal. Conversely, in the event
that PWD mode is not selected, int4 may be used as a PIO.
2.2.22 lcs_n/once0_n—Lower Memory Chip Select (synchronous output with internal
The lcs_n pin provides an indication that a memory access is in progress to the lower memory
block. The size of the Lower Memory Block and its base address are programmable, with the
size adjustable up to 512 Kbytes. The lcs_n may be configured for either an 8- or 16-bit bus
width for the IA186ES microcontroller by the Auxiliary Configuration Register (AUXCON Bit
[2]) and is held high during bus hold.
The once0_n pin (ON Circuit Emulation) and its companion pin once1_n define the
microcontroller mode during reset. These two pins are sampled on the rising edge of res_n and if
both are asserted low the microcontroller starts in ONCE mode, else it starts normally. In ONCE
mode, all pins are tristated and remain so until a subsequent reset. To prevent the
microcontroller from entering ONCE mode inadvertently, this pin has a weak pullup that is only
present during reset. Finally this pin is not tristated during bus hold.
2.2.23 mcs0_n/pio14—Midrange Memory Chip Select (synchronous output with internal
The mcs0_n pin provides an indication that a memory access is in progress to the midrange
memory block. The size of the Midrange Memory Block and its base address are programmable.
The mcs0_n may be configured for either an 8- or 16-bit bus width for the IA186ES
microcontroller by the Auxiliary Configuration Register (AUXCON Bit [1]) and is held high
during bus hold. The mcs0_n may be programmed as the chip select for the whole middle chip
select address range. Furthermore, this pin has a weak pullup that is only present during reset.
2.2.24 mcs2_n–mcs1_n (pio24–pio 15)—Midrange Memory Chip Selects (synchronous
The mcs2_n and mcs1_n pins provide an indication that a memory access is in progress to the
second or third midrange memory block. The size of the Midrange Memory Block and its base
address are programmable. The mcs2_n and mcs1_n may be configured for either an 8- or 16-bit
bus width for the IA186ES microcontroller by the Auxiliary Configuration Register (AUXCON
Bit [1]) and are held high during bus hold. Furthermore, these pins have weak pullups that are
pullup)/ONCE Mode Request (input)
pullup)
outputs with internal pullup)
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Page 37 of 154
IA211050902-15
December 24, 2008
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