ia186es Innovasic Semiconductor Inc., ia186es Datasheet - Page 40

• Manufacturer Part Number: ia186es
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
2.2.30 pcs5_n/A1/pio3—Peripheral Chip Select 5 (synchronous output)/Latched Address
The pcs5_n signal provides an indication that a memory access is under way for the sixth region
of the peripheral memory block (I/O or memory address space). The base address of the
peripheral memory block is programmable. The pcs5_n is held high during both bus hold and
reset. This output is asserted with the ad address bus over a 256-byte range.
The A1 pin provides and internally latched address Bit [1] to the system when the EX bit
(Bit [7]) in the mcs_n and pcs_n auxiliary (MPCS) register is 0. It retains its previously latched
value during a bus hold.
2.2.31 pcs6_n/A2/pio2—Peripheral Chip Select 6 (synchronous output)/Latched Address
The pcs6_n signal provides an indication that a memory access is underway for the seventh
region of the peripheral memory block (I/O or memory address space). The base address of the
peripheral memory block is programmable. The pcs6_n is held high during both bus hold and
reset. This output is asserted with the ad address bus over a 256-byte range.
The A2 pin provides an internally latched address Bit [2] to the system when the EX bit (Bit [7])
in the MPCS register is 0. It retains its previously latched value during a bus hold.
2.2.32 pio31–pio0—Programmable I/O Pins (asynchronous input/output open-drain)
There are 32 individually PIO pins provided.
2.2.33 rd_n—Read strobe (synchronous output with tristate)
This pin provides an indication to the system that a memory or I/O read cycle is underway. It
will not to be asserted before the ad bus is floated during the address to data transition. The rd_n
is tristated during bus hold.
2.2.34 res_n—Reset (asynchronous level-sensitive input)
This pin forces a reset on the microcontroller. It has a Schmitt trigger to allow POR generation
via an RC network. When this signal is asserted, the microcontroller immediately terminates its
present activity, clears its internal logic, and transfers CPU control to the reset address, FFFF0h.
The res_n must be asserted for at least 1 ms and may be asserted asynchronously to clkouta as it
is synchronized internally. Furthermore, v
stable for more than four of its clock periods for the period that res_n is asserted. The
microcontroller starts to fetch instructions 6.5 clkouta clock periods after the deassertion of
res_n.
Bit [1] (synchronous output)
Bit [2] (synchronous output)
®
UNCONTROLLED WHEN PRINTED OR COPIED
cc
must be within specification and clkouta must be
Page 40 of 154
IA211050902-15
December 24, 2008
http://www.Innovasic.com
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