ia186es Innovasic Semiconductor Inc., ia186es Datasheet - Page 92

• Manufacturer Part Number: ia186es
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
5.1.31 T2CON (066h)
Timer2 Mode and CONtrol Registers. This register controls the operation of the Timer2. The
value of the T2CON register is 0000h at reset (see Table 52).
Table 52. Timer2 Mode and Control Registers
EN
15
INHn
Bit [3]—P Prescaler Bit → P is ignored if external clocking is enabled (EXT = 1). Timer
2 prescales the timer when P is set to 1. Otherwise, the timer is incremented on every
fourth CLKOUT cycle.
Bit [2]—EXT External Clock Bit → This bit determines whether an external or internal
clock is used. If EXT = 1, an external clock is used. If EXT = 0, an internal is used.
Bit [1]—ALT Alternate Compare Bit → If set to 1, the timer will count to maxcount
compare register A, reset the count register to 0, and then count to maxcount compare
register B, reset the count register to 0, and begin again at maxcount compare register A.
If set to 0, the timer will count to maxcount compare register A, reset the count register
to 0, and begin again at maxcount compare register A. Maxcount compare register B is
not used in this case.
Bit [0]—CONT Continuous Mode Bit → The timer will run continuously when this bit is
set to 1. The timer will stop after each count run and EN will be cleared if the CONT bit
is set to 0. If CONT = 1 and ALT = 1, the respective timer counts to the maxcount
compare A value and resets, then it commences counting to maxcount compare B value,
resets and ceases counting.
Bit [15]—EN Enable Bit → The timer is enabled when the EN bit is 1. The timer count
is inhibited when the EN bit is 0. Setting this bit to 1 by writing to the T2CON register
requires that the INH bit be set to 1 during the same write. This bit is write-only, but with
the INHn bit set to 1 in the same write operation.
Bit [14]—INH Inhibit Bit → Gates the setting of the enable (EN) bit. This bit must be
set to 1 in the same write operation that sets the enable (EN) bit. This bit always reads
as 0.
Bit [13]—INT Interrupt Bit → An interrupt request is generated when the Count register
reaches its maximum, MC = 1, by setting the INT bit to 1.
Bits [12–6]—Reserved. Set to 0.
14
INT
13
12
0
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11
0
10
0
9
0
8
0
UNCONTROLLED WHEN PRINTED OR COPIED
7
0
6
0
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December 24, 2008
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