ia186es Innovasic Semiconductor Inc., ia186es Datasheet - Page 60

• Manufacturer Part Number: ia186es
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
The current count of timer1 for INT2 and timer0 for INT4 should be inspected by the ISR to
determine the pulse width. The timer count register should then be reset by the ISR in readiness
for the next pulse.
The timer count rate (one-fourth of the processor clock rate) determines the maximum resolution
of the timers. To avoid the delay in servicing a timer interrupt in cases where the pulse width is
short, the INT2 and INT4 request bits in the Interrupt Request register may be polled. In cases
where the pulse width is greater than the maximum count of the timer, detection is achieved
either by monitoring the Maximum Count (MC) bit of the respective timer or by enabling the
timer interrupt requests by setting the INT bit in the respective Timer Mode and Control
Register.
4.25
There are two independent asynchronous serial ports that employ standard industry
communication protocols in their implementation of full duplex, bi-directional data transfers.
Functioning independently, either port may be the source or destination of DMA transfers.
The following features are supported:
4.26
Thirty-two pins are programmable as I/O signals (PIO). Table 15 presents them in both numeric
and alphabetic order. Because programming a pin as a PIO disables its normal function, it
should be done only if the normal function is not required. A PIO pin can be programmed as an
Asynchronous Serial Ports
Full-duplex data transfers
7-, 8-, or 9-bit data transfers
Odd, even, or no parity
One or two stop bits
Break characters of two lengths
Error detection provided by parity, framing, or overrun errors
Hardware handshaking achieved with the following selectable control signals:
– Clear to send (cts_n)
– Enable receiver request (enrx_n)
– Ready to send (rts_n)
– Ready to receive (rtr_n)
DMA to and from the ports
Each port has its own maskable interrupts
9-bit multidrop protocol
Each port has an independent baud-rate generator
Maximum baud rate is 1/16 of the processor clock
Transmit and receive lines are double buffered
Programmable I/O
®
UNCONTROLLED WHEN PRINTED OR COPIED
Page 60 of 154
IA211050902-15
December 24, 2008
http://www.Innovasic.com
Customer Support:
Data Sheet
1-888-824-4184