ia186es Innovasic Semiconductor Inc., ia186es Datasheet - Page 86

• Manufacturer Part Number: ia186es
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
Bit [10]—TB8 Transmit Bit 8 → This is the ninth data bit transmitted when in modes 2
and 3. This bit is cleared at each transmitted word and is not buffered. To transmit data
with this bit set high, the following procedure is recommended.
1. The TEMT bit in the serial port status register must go high.
2. Set the TB8 bit by writing it to the serial port control register.
3. Write the transmit character to the serial port transmit register.
Bit [9]—FC Flow Control Enable → This bit controls the hardware handshake (flow
control) by enabling it when set to 1, and vice versa. The type of flow control depends on
the value of the ENRX0/ENRX1 and RTS0/RTS1 bits in the AUXCON register.
– Serial Port 0 is a special case in that, if this bit is 1, the associated pins are used for
– This bit is 0 at reset.
Bit [8]—TXIE Transmitter Ready Interrupt Enable → This bit enables the generation of
an interrupt request whenever the transmit holding register is empty (THRE Bit [1]). The
respective port does not generate interrupts when this bit is 0. Interrupts continue to be
generated as long as THRE and the TXIE are 1.
Bit [7]—RXIE Receive Data Ready Interrupt Enable → This bit enables the generation of
an interrupt request whenever the receive register contains valid data (RDR Bit [1]). The
respective port does not generate interrupts when this bit is 0. Interrupts continue to be
generated as long as RDR and the RXIE are 1.
Bit [6]—TMODE Transmit Mode → The transmit section of the serial port is enabled
when this bit is 1. Conversely, the transmit section of the serial port is disabled when this
bit is 0.
Bit [5]—RMODE Receive Mode → The receive section of the serial port is enabled
when this bit is 1. Conversely, the receive section of the serial port is disabled when this
bit is 0.
Bit [4]—EVN Even Parity → When this bit is 1, even parity protocol is established.
Conversely, odd parity is established when this bit is 0. This bit is valid only when parity
is enabled (PE).
Bit [3]—PE Parity Enable → Parity is enabled when this bit is 1 and disabled when this
bit is 0.
Bit [2–0]—MODE Mode of Operation → These three bits establish the mode of
operation of the respective serial port. The valid modes and their functions are shown
below.
flow control overriding the Peripheral Chip Select signals.
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Page 86 of 154
IA211050902-15
December 24, 2008
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