mt9075bpr1 Zarlink Semiconductor, mt9075bpr1 Datasheet - Page 22

• Manufacturer Part Number: mt9075bpr1
• Description: E1 Single Chip Transceiver With Liu
• Manufacturer: Zarlink Semiconductor

HDLC Frame Structure
A valid HDLC frame (also referred as “packet”) begins with an opening flag, contains at least 16 bits of data
field, and ends with a 16 bit FCS followed by a closing flag (Table 9).
All HDLC frames start and end with a unique flag sequence “01111110
flags and appends them to the packet to be transmitted. The receiver searches the incoming data stream for the
flags on a bit-by-bit basis to establish frame synchronization.
The data field usually consists of an address field, control field and information field. The address field consists of
one or two bytes directly following the opening flag. The control field consists of one byte directly following the
address field. The information field immediately follows the control field and consists of n bytes of data. The HDLC
does not distinguish between the control and information fields and a packet does not need to contain an
information field to be valid.
The FCS field, which precedes the closing flag, consists of two bytes. A cyclic redundancy check utilizing the
CCITT standard polynomial “X
all bits of the address and data field. The complement of the FCS is transmitted, most significant bit first, in the FCS
field. The receiver calculates the FCS on the incoming packet address, data and FCS field and compares the result
to “F0B8”. If no transmission errors are detected and the packet between the flags is at least 32 bits in length then
the address and data are entered into the receive FIFO minus the FCS which is discarded.
Data Transparency (Zero Insertion/Deletion)
Transparency ensures that the contents of a data packet do not imitate a flag, go-ahead, frame abort or idle
channel. The contents of a transmitted frame, between the flags, is examined on a bit-by-bit basis and a 0 is
inserted after all sequences of 5 contiguous 1s (including the last five bits of the FCS). Upon receiving five
contiguous 1s within a frame the receiver deletes the following 0.
Invalid Frames
A frame is invalid if one of the following four conditions exists:
•
•
•
•
Frame Abort
The transmitter will abort a current packet by substituting a zero followed by seven contiguous 1s in place of the
normal packet. The receiver will abort upon reception of seven contiguous 1s occurring between the flags of a
packet which contains at least 26 bits.
If the FCS pattern generated from the received data does not match the “F0B8” pattern then the last data
byte of the packet is written to the received FIFO with a ‘bad packet’ indication.
A short frame exists if there are less than 25 bits between the flags. Short frames are ignored by the receiver
and nothing is written to the receive FIFO.
Packets which are at least 25 bits in length but less than 32 bits between the flags are also invalid. In this
case the data is written to the FIFO but the last byte is tagged with a “bad packet” indication.
If a frame abort sequence is detected the packet is invalid. Some or all of the current packet will reside in the
receive FIFO, assuming the packet length before the abort sequence was at least 26 bits long.
16
Flag (7EH)
One Byte
01111110
Opening
+X
12
+X
5
Table 9 - HDLC Frame Format
+1” produces the 16-bit FCS. In the transmitter the FCS is calculated on
Zarlink Semiconductor Inc.
n Bytes
Field
Data
n ≥ 2
MT9075B
22
Bytes
FCS
Two
Flag (7EH)
2
One Byte
01111110
” (7EH). The transmitter generates these
Closing
Data Sheet