mt9075bpr1 Zarlink Semiconductor, mt9075bpr1 Datasheet - Page 6

• Manufacturer Part Number: mt9075bpr1
• Description: E1 Single Chip Transceiver With Liu
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
PLCC MQFP
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
Pin #
23
24
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
RxFP/Rx6
GND
VDD
TRING
BS/LS
Name
RxMF
4KCK
TTIP
Tms
E2o
C4b
Tdo
Tclk
Trst
F0b
V
V
Tdi
IC
SS
DD
ATx
ATx
Receive Multiframe Boundary (Output). An output pulse delimiting the received
multiframe boundary. The next frame output on the data stream (DSTo) is basic frame
zero on the PCM 30 link. This receive multiframe signal can be related to either the
receive CRC multiframe (page 01H, address 10H, bit 6, MFSEL=1) or the receive
signalling multiframe (MFSEL=0).
System Bus Synchronous/Line Synchronous Selection (Input). If high, C4b and F0b
will be inputs; if low, C4b and F0b will be outputs.
2.048 MHz Extracted Clock (Output). The clock extracted from the received signal
and used internally to clock in data received on RTIP and RRING.
4.096 MHz System Clock (Input/Output). C4b is the clock for the ST-BUS sections and
transmit serial PCM data of the MT9075B. In the free-run (BL/FR=0) or line synchronous
mode (BL/FR=1 and BS/LS=0) this signal is an output, while in the system bus
synchronous mode (BS/LS=1) this signal is an input clock.
Frame Pulse (Input/Output). This is the ST-BUS or GCI frame synchronization
signal, which delimits the 32 channel frame of CSTi, CSTo, DSTi, DSTo and the
PCM30 link. In the free-run (BL/FR=0) or loop synchronous mode (BL/FR=1 and
BS/LS=0) this signal is an output, while in the Bus Synchronous mode (BL/FR=1 and
BS/LS=0) this signal is an input. The GCI/ST-BUS selection is made under software
control. Page 02H, address 13H, bit 0, GCI/ST=1 selects GCI frame pulse; GCI/ST=0
selects ST-BUS.
Receive Frame Pulse/Receive CCS Clock (Output). An 8 kHz pulse signal, which is
low for one extracted clock period. This signal is synchronized to the receive PCM 30
basic frame boundary.
When 64KCCS (page 01H, address 1AH, bit 0) is set to 1, this pin outputs a 64 kHz clock
derived by dividing down the extracted 2.048 MHz clock. This clock is used to clock CCS
data out of pin CSTo in the CCS mode.
Internal Connection. Must be left open for normal operation.
Negative Power Supply (Input). Digital ground.
Positive Power Supply (Input). Digital supply (+5V ± 5%).
Transmit Analog Power Supply (Input). Analog supply for the LIU transmitter (+5V ±
5%).
Transmit TIP and RING (Outputs). Differential outputs for the transmit line signal - must
be transformer coupled (See Figure 4).
Transmit Analog Ground (Input). Analog ground for the LIU transmitter.
IEEE 1149.1 Test Data Input. If not used, this pin should be pulled high.
IEEE 1149.1 Test Data Output. If not used, this pin should be left unconnected.
IEEE 1149.1 Test Mode Selection (Input). If not used, this pin should be pulled high.
IEEE 1149.1 Test Clock Signal (Input). If not used, this pin should be pulled high.
IEEE 1149.1 Reset Signal (Input). If not used, this pin should be held low.
Zarlink Semiconductor Inc.
MT9075B
6
Description
Data Sheet