mt9075bpr1 Zarlink Semiconductor, mt9075bpr1 Datasheet - Page 26

• Manufacturer Part Number: mt9075bpr1
• Description: E1 Single Chip Transceiver With Liu
• Manufacturer: Zarlink Semiconductor

signals may jitter or wander with respect to the synchronizing trunk signal. Therefore, the E2o clocks of non-
synchronizer trunks may wander with respect to the E2o clock of the synchronizer and the system bus.
Network standards state that, within limits, trunk interfaces must be able to receive error-free data in the presence
of jitter and wander (refer to network requirements for jitter and wander tolerance). The MT9075B will allow a
maximum of 26 channels (208 UI, unit intervals) of wander and low frequency jitter before a frame slip will occur.
The minimum delay through the receive slip buffer is approximately two channels and the maximum delay is
approximately 60 channels (see Figure 9).
When the C4b and the E2o clocks are not phase-locked, the rate at which data is being written into the slip buffer
from the PCM 30 side may differ from the rate at which it is being read out onto the ST-BUS. If this situation
persists, the delay limits stated in the previous paragraph will be violated and the slip buffer will perform a controlled
frame slip. That is, the buffer pointers will be automatically adjusted so that a full PCM 30 frame is either repeated
or lost. All frame slips occur on PCM 30 frame boundaries.
Two status bits, RSLIP and RSLPD (page 03H, address 15H), give indication of a slip occurrence and direction.
RSLIP changes state in the event of a slip. If RSLPD=0, the slip buffer has overflowed and a frame was lost; if
RSLPD=1, a underflow condition occurred and a frame was repeated. A maskable interrupt SLPI (page 01H,
address 1BH) is also provided.
Figure 9 illustrates the relationship between the read and write pointers of the receive slip buffer. Measuring
clockwise from the write pointer, if the read pointer comes within two channels of the write pointer a frame slip will
occur, which will put the read pointer 34 channels from the write pointer. Conversely, if the read pointer moves more
than 60 channels from the write pointer, a slip will occur, which will put the read pointer 28 channels from the write
pointer. This provides a worst case hysteresis of 13 channels peak (26 channels peak-to-peak) or a wander
tolerance of 208 UI.
Framing Algorithm
The MT9075B contains three distinct framing algorithms: basic frame alignment, signalling multiframe alignment
and CRC-4 multiframe alignment. Figure 10 is a state diagram that illustrates these algorithms and how they
interact.
After power-up, the basic frame alignment framer will search for a frame alignment signal (FAS) in the PCM 30
receive bit stream. Once the FAS is detected, the corresponding bit 2 of the non-frame alignment signal (NFAS) is
checked. If bit 2 of the NFAS is zero a new search for basic frame alignment is initiated. If bit 2 of the NFAS is one
Read Pointer
47 CH
Read Pointer
60 CH
34 CH
512 Bit
Elastic
Store
Write Pointer
Figure 9 - Read and Write Pointers in the Slip Buffers
28 CH
2 CH
Read Pointer
Read Pointer
15 CH
Zarlink Semiconductor Inc.
MT9075B
-13 CH
26
13 CH
Wander Tolerance
Data Sheet