mt9075bpr1 Zarlink Semiconductor, mt9075bpr1 Datasheet - Page 34

• Manufacturer Part Number: mt9075bpr1
• Description: E1 Single Chip Transceiver With Liu
• Manufacturer: Zarlink Semiconductor

•
The alarm reporting latch (address 1BH page 04H) contains a register whose bits are set high for selected alarms.
These bits stay high until the register is read. This allows the controller to record intermittent or sporadic alarm
occurrences.
Automatic Alarms
The transmission of RAI and signalling multiframe alarms can be made to function automatically from control bits
ARAI and AUTY (page 01H, address 11H) When ARAI = 0 and basic frame synchronization is lost (page 03H,
address 10H, bit 7, SYNC = 1), the MT9075 will automatically transmit the RAI alarm signal to the far end of the
link. The transmission of this alarm signal will cease when basic frame alignment is acquired.
When AUTY = 0 and signalling multiframe alignment is not acquired (page 03H, address 10H, bit 6, MFSYNC = 1),
the MT9075 will automatically transmit the multiframe alarm (Y-bit) signal to the far end of the link. This
transmission will cease when signalling multiframe alignment is acquired.
Interrupts
The MT9075B has an extensive suite of maskable interrupts, which are divided into eight categories based on the
type of event that caused the interrupt. Each interrupt category has an associated interrupt vector described in
Table 11. When unmasked interrupts occur, IRQ will go low and one or more bits of the interrupt vector IV7-IV0
(page 04H, address 12H) will go high. After the interrupt vector is read it is automatically cleared and IRQ will return
to a high impedance state. The interrupt acknowledgment function can also be accomplished by toggling the INTA
bit (page 01H, address 1AH).
All the interrupts of the MT9075B are maskable. This is accomplished through the corresponding interrupt mask
words on page 01H (except for the HDLC interrupt mask registers which are located on page 0BH and 0CH).
National Use Bit Interrupt Mask Word (address 19H)
Bit 7
Interrupt Mask Word Zero (address 1BH)
Bit 7
Interrupt Mask Word One (address 1CH)
Bit 7
Interrupt Mask Word Two (address 1DH)
Bit 7
- - -
SYNI
EBO
T2 - (T2 timer bit on page 03H address 12H) this status bit (and maskable interrupt) shall be high when a
normal signal has been received for a minimum of 10 msec. This bit will be low when an abnormal signal is
being received.
EBI
PRBSO
CRCO
CRCI
RAII
PRBS
CALNI
AISI
CEFI
SanibI
AISI6I
FERO
BPVI
SabitI
LOSI
RCR1
JAI
C8Sa6I
Zarlink Semiconductor Inc.
FERI
RCR0
BERO
MT9075B
Sa6I
BPVO
AUXPI
BERI
34
Sa5I
Bit 0
SLPI
CMFO
SIGI
Bit 0
Bit 0
Bit 0
Data Sheet