mt9075bpr1 Zarlink Semiconductor, mt9075bpr1 Datasheet - Page 8

• Manufacturer Part Number: mt9075bpr1
• Description: E1 Single Chip Transceiver With Liu
• Manufacturer: Zarlink Semiconductor

The digital portion of the MT9075B connects an incoming stream of time multiplexed PCM channels (at
2.048 Mbit/s) to the transmit payload of the E1 trunk, while the receive payload is connected to the ST-BUS or GCI
2.048 Mbit/s backplane bus for both data and signalling. Control, reporting and conditioning of the line is
implemented via a parallel microprocessor interface. The MT9075B framing algorithm allows automatic
interworking between CRC-4 and non-CRC-4 interfaces.
The S
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The MT9075B operates in either termination or transparent modes selectable via software control. In the
termination mode the CRC-4 calculation is performed as part of the framing algorithm. In the transmit transparent
mode, no framing or signalling is imposed on the data transmit from DSTi on the line. In addition, the MT9075B
optionally allows the data link maintenance channel to be modified and updates the CRC-4 remainder bits to reflect
the modification. All channel, framing and signalling data passes through the device unaltered. This is useful for
intermediate point applications of a PCM 30 link where the data link data is modified, but the error information
transported by the CRC-4 bits must be passed to the terminating end. In the receive transparent mode, the
received line data is channelled to DSTo with framing operations disabled, consequently, the data passes through
the slip buffer and drives DSTo with an arbitrary alignment.
The MT9075B has a comprehensive suite of status, alarm, performance monitoring and reporting features. These
include counters for BPVs, CRC errors, E-bit errors, errored frame alignment signals, BERT, and RAI and
continuous CRC errors. Also, included are transmission error insertion for BPVs, CRC-4 errors, frame and non-
frame alignment signal errors, payload errors and loss of signal errors.
A complete set of loopback functions is provided, which includes digital, remote, ST-BUS, payload, metallic, local
and remote time slot.
The MT9075B also contains a comprehensive set of maskable interrupts and an interrupt vector function. Interrupt
sources consist of synchronization status, alarm status, counter indication and overflow, timer status, slip indication,
maintenance functions and receive channel associated signalling bit changes. A special set of maskable interrupts
have been included for sensing changes in the state of the national use bits and nibbles, in compliance to emerging
ETS requirements.
The MT9075B system timing may be slaved to the line, operated in freerun mode, or controlled by an external
timing source.
Functional Description
MT9075B Line Interface Unit (LIU)
Receiver
The receiver portion of the MT9075B LIU consists of an input signal peak detector, an optional two-stage equalizer,
a smoothing filter, adaptive threshold comparators, data and clock slicers, and a clock extractor. Receive
equalization gain can be set via software control or it can be determined automatically by the peak detectors.
The output of the receive equalizer is conditioned by a smoothing filter and is passed on to the clock and data slicer.
The clock slicer output signal drives a phase locked loop, which generates the extracted clock (E2o). This extracted
clock is used to sample the output of the data comparator.
The LOS output pin (pin 61 in PLCC, pin 57 in MQFP) is user selectable, by setting control bit LOS/LOF (page 02H,
register 13H, bit 2), to indicate a loss of signal or loss of basic frame synchronization condition. In addition, a status
Single byte registers;
Five byte transmit and receive national bit buffers;
Data link pins TxDL, RxDL, RxDLCLK and TxDLCLK;
HDLC Controller with a 128 byte FIFO.
a
bits can be accessed by the MT9075B in the following four ways:
Zarlink Semiconductor Inc.
MT9075B
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Data Sheet