mt9075bpr1 Zarlink Semiconductor, mt9075bpr1 Datasheet - Page 29

• Manufacturer Part Number: mt9075bpr1
• Description: E1 Single Chip Transceiver With Liu
• Manufacturer: Zarlink Semiconductor

Channel Signalling
When control bit TxCCS (page 01H, address 1AH) is set to one, the MT9075B is in Common Channel Signalling
(CCS) mode. When TxCCS is low it is in Channel Associated Signalling mode (CAS). The CAS mode ABCD
signalling nibbles can be passed either via the micro-ports (when page 01H, address 1AH, bit 3, RPSIG = 1) or
through related channels of the CSTo and CSTi serial links (when RPSIG = 0). Memory page 05H contains the
receive ABCD nibbles and page 06H the transmit ABCD nibbles for micro-port CAS access.
In CAS operation an ABCD signalling bit debounce of 14 msec. can be selected by writing a one to DBNCE (page
02H, address 10H, bit 0)). This is consistent with the signalling recognition time of ITU-T Q.422. It should be noted
that there may be as much as 2 msec. added to this duration because signalling equipment state changes are not
synchronous with the PCM 30 multiframe.
If multiframe synchronization is lost (page 03H, address 10H, bit 6, MFSYNC = 1) all receive CAS signalling nibbles
are frozen. Receive CAS nibbles will become unfrozen when multiframe synchronization is acquired.
When the CAS signalling interrupt is unmasked (page 01H, address 1CH, bit 0, SIGI=1), pin IRQ (pin 12 in PLCC,
85 in MQFP) will become active when a signalling nibble state change is detected in any of the 30 receive
channels. The SIGI interrupt vector (page 04H, address 12H) is 01H.
In CCS mode the data transmit on channel 16 is either sourced from channel 16 data on DSTi or from the pin
CSTi. If 64KCCS (page 01H, address 1AH, bit 0) is zero the data is sourced from DSTi. If 64KCCS is high data
destined for channel 16 is clocked in from CSTi (pin 6 in PLCC, pin 71 in MQFP) with an internal 64 KHz clock
divided down from C4b. Data received from channel 16 is clocked out on CSTo (pin 5 in PLCC, pin 70 in
MQFP). By dividing down the extracted 2.048 MHz clock, a 64 kHz receive clock synchronous with the data is
created. This signal is output on Rx64KCK (pin 47 in PLCC, pin 35 in MQFP).
Loopbacks
In order to meet PRI Layer 1 requirements and to assist in circuit fault sectionalization, the MT9075B has six
loopback functions. The control bits for digital, remote, ST-BUS, payload and metallic loopbacks are located on
page 01H, address 15H. The remote and local time slot loopbacks are controlled through control bits 5 and 4 of the
Per Time Slot Control Words on pages 07H and 08H.
a) Digital Loopback (DG Loop) - DSTi to DSTo at the framer LIU interface. Bit DLBK = 0 normal; DLBK = 1
activate.
b) Remote Loopback (RM Loop) - RTIP and RRING to TTIP and TRING respectively at the PCM 30 side. Bit
RLBK = 0 normal; RLBK = 1 activate.
c) ST-BUS Loopback (ST Loop) - DSTi to DSTo at the system side. Bit SLBK = 0 normal; SLBK = 1 activate.
System
System
DSTo
DSTo
DSTi
Zarlink Semiconductor Inc.
MT9075B
MT9075B
MT9075B
29
Tx
Tx
Rx
PCM30
PCM30
Data Sheet