mt9075bpr1 Zarlink Semiconductor, mt9075bpr1 Datasheet - Page 75

• Manufacturer Part Number: mt9075bpr1
• Description: E1 Single Chip Transceiver With Liu
• Manufacturer: Zarlink Semiconductor

7 - 0
Bit
1-0
Bit
7
6
5
4
3
2
Mark-Idle
Name
Adrec
RxEN
TxEN
Name
EOP
RSV
(00)
Bit7
Bit0
(0)
(0)
(0)
(0)
FA
(0)
(0)
-
Address Recognition. When one this bit will enable address recognition.
This forces the receiver to recognize only those packets having the unique
address as programmed in the Receive Address Recognition Registers or if
the address is an All call address.
Receive Enable. When one the receiver will be immediately enabled and
will begin searching for flags, Go-Aheads etc.
When zero this bit will disable the HDLC receiver after the rest of the packet
presently being received is finished. The receiver internal clock is disabled.
Transmit Enable. When one the transmitter will be immediately enabled
and will begin transmitting data, if any, or go to a mark idle or interframe
time fill state.
When zero this bit will disable the HDLC transmitter after the completion of
the packet presently being transmitted. The transmitter internal clock is
disabled.
End Of Packet. Forms a tag on the next byte written the TX FIFO, and
when set will indicate an end of packet byte to the transmitter, which will
transmit an FCS following this byte. This facilitates loading of multiple
packets into TX FIFO. Reset automatically after a write to the TX FIFO
occurs.
Frame Abort. Forms a tag on the next byte written to the TX FIFO, and
when set to one FA will indicate to the transmitter that it should abort the
packet in which that byte is being transmitted. Reset automatically after a
write to the TX FIFO.
When zero, the transmitter will be in an idle state. When one it is in an
interframe time fill state. These two states will only occur when the TX FIFO
is empty.
Reserved: Must be set to 0 for normal operation.
This is the received data byte read from the RX FIFO. The status bits of
this byte can be read from the status register. The FIFO status is not
changed immediately when a write or read occurs. It is updated after the
data and the read/write pointers have settled.
Table 87 - HDLC Control Register 1
Table 86 - RX FIFO Read Register
(Page 0BH &0CH, Address 13H)
(Pages 0BH & 0CH, Address 12H)
Zarlink Semiconductor Inc.
MT9075B
75
Functional Description
Functional Description
Data Sheet