kfm2g16q2m-deb8 Samsung Semiconductor, Inc., kfm2g16q2m-deb8 Datasheet - Page 101

• Manufacturer Part Number: kfm2g16q2m-deb8
• Description: 2gb Muxonenand M-die
• Manufacturer: Samsung Semiconductor, Inc.

NO
3.8.1 Interleaving Cache Read
Interleaving Cache Read flow chart
MuxOneNAND2G(KFM2G16Q2M-DEBx)
MuxOneNAND4G(KFN4G16Q2M-DEBx)
MuxOneNAND8G(KFK8G16Q2M-DEBx)
The Interleving Cache Read use for reading data which writed by 2X Interleaving Cache Program.
Note 1) DBS must be set before data input.
Add: F103h DQ=FCPA, FCSA
DQ[15]=Ongo & DQ[13]=Load
Write ’Cache Read’ Command
Write ’FCPA, FCSA’ of Flash
Write ’BSA, BSC’ of Flash
Write 0 to Interrupt register
Add: F200h DQ=BSA, BSC
Add: F103h DQ=FCPA, FCSA
Write ’FCPA, FCSA’ of Flash
Add: F107h DQ=FPA, FSA
Add: F100h DQ=DFS, FBA
Write ’BSA, BSC’ of Flash
Add: F200h DQ=BSA, BSC
Select DataRAM for DDP
Write ’DFS, FBA’ of Flash
Write ’FPA, FSA’ of Flash
DQ[15]=1 & DQ[13]=1 ?
Add: F102h DQ=FCBA
Add: F241h DQ=0000h
Add: F220h DQ=000Eh
Write ’FCBA’ of Flash
Add: F102h DQ=FCBA
Write ’FCBA’ of Flash
Add: F101h DQ=DBS
Read Controller
Status Register
2) FBA must be an even block.
3) These registers must be set as BSA=1000, BSC=00 and FSA=00.
4) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter
Add: F240h
2.8.18.1.
Start
YES
3)
1)
3)
3)
2)
4)
NO
Write ’Cache Read’ Command
DQ[15]=Ongo & DQ[13]=Load
Write 0 to Interrupt register
Add: F100h DQ=DFS, FBA
Add: F100h DQ=DFS, FBA
Add: F107h DQ=FPA, FSA
Select DataRAM for DDP
Select DataRAM for DDP
Write ’DFS, FBA’ of Flash
Write ’DFS, FBA’ of Flash
Write ’FPA, FSA’ of Flash
Add: F240h DQ[10]=Error
Add: F241h DQ[15]=INT
DQ[15]=1 & DQ[13]=1 ?
Add: F241h DQ=0000h
Wait for INT high State
Add: F220h DQ=000Eh
Add: F101h DQ=DBS
Add: F101h DQ=DBS
Read Controller
Status Register
Read Controller
Status Register
YES
Add: F240h
DQ[10] = 0 ?
NO
Map Out
1)
YES
1)
3)
2)
2)
4)
101
NO
Write ’Cache Read’ Command
Write 0 to Interrupt register
Host reads data from DataRAM
Host reads data from DataRAM
Write 0 to Interrupt register
Add: F107h DQ=FPA, FSA
Write ’FPA, FSA’ of Flash
Add: F100h DQ=DFS, FBA
(n-1)th command issue?
Write ’Finish Cache Read
Add: F240h DQ[10]=Error
Write ’DFS, FBA’ of Flash
Add: F241h DQ=0000h
Command’@Final Read
Add: F220h DQ=000Eh
Add: F241h DQ=0000h
Add: F220h DQ=000Ch
Add: F241h DQ[15]=INT
Host reads data from
Wait for INT high State
Read Controller
Status Register
NO
Done with
DQ[10] = 0 ?
DataRAM
3)
4)
4)
2)
FLASH MEMORY
YES
NO
NO
Host reads data from DataRAM
Host reads data from DataRAM
Write 0 to Interrupt register
* DBS, DFS is for DDP
Select DataRAM for DDP
Add: F240h DQ[10]=Error
Write ’Finish Cache Read
Add: F240h DQ[10]=Error
Add: F241h DQ[15]=INT
Command’@Final Read
Add: F241h DQ=0000h
Add: F220h DQ=000Ch
Wait for INT high State
Add: F241h DQ[15]=INT
Add: F101h DQ=DBS
Wait for INT high State
Read Controller
Status Register
Read Controller
Status Register
DQ[10] = 0 ?
DQ[10] = 0 ?
END
YES
YES
1)
4)