kfm2g16q2m-deb8 Samsung Semiconductor, Inc., kfm2g16q2m-deb8 Datasheet - Page 99

• Manufacturer Part Number: kfm2g16q2m-deb8
• Description: 2gb Muxonenand M-die
• Manufacturer: Samsung Semiconductor, Inc.

Cache Read Flow Chart
MuxOneNAND2G(KFM2G16Q2M-DEBx)
MuxOneNAND4G(KFN4G16Q2M-DEBx)
MuxOneNAND8G(KFK8G16Q2M-DEBx)
No
Note 1) In case of first cycle cache read, BSA must be set to 1000 or 1100, and from second cycle cache read,
Write ‘ Cache Read’ Command
DQ[15]=Ongo & DQ[13]=Load
Write ‘FCPA, FCSA
Add: F103h DQ=FCPA, FCSA
Write ‘BSA
Write 0 to Interrupt register
Write ’DFS*, FBA’ of Flash
Add: F100h DQ=DFS, FBA
Add: F200h DQ=BSA, BSC
Select DataRAM for DDP
Write ‘FPA, FSA
Add: F107h DQ=FPA, FSA
Read Controller Status
DQ[15]=1 & DQ[13]=1 ?
2) BSC, FSA and FCSA must be set to "00".
3) These steps can also be set during INT=High, before next ’Cache Read Command’
4) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
5) When host reads data from DataRAM, host should start from the DataRAM of the first set BSA, and then next DataRAM
Register Add: F240h
Add: F102h DQ=FCBA
Add: F241h DQ=0000h
Add: F220h DQ=000Eh
Write ‘FCBA’ of Flash
Add: F101h DQ=DBS
BSA will automatically be switched between DataRAM0 and DataRAM1.
alternately, as the number of Cache Read.
1)
Start
, BSC
2)
Yes
2)
2)
’ of Flash
’ of Flash
’ of Flash
3)
4)
Write ‘ Cache Read’ Command
Write ’DFS*, FBA’ of Flash
Write ‘FPA, FSA
Write 0 to Interrupt register
Add: F107h DQ=FPA, FSA
(n-1)th command issue?
Add: F240h DQ[10]=Error
Add: F241h DQ[15]=INT
Read Controller Status
Wait for INT high State
Add: F241h DQ=0000h
Add: F100h DQ=FBA
Add: F220h DQ=000Eh
Host reads data from
Done with
DQ[10]=0?
DataRAM
Yes
Register
99
No
2)
’ of Flash
5)
3)
3)
4)
Yes
No
Map out
No
No
Write 0 to Interrupt register
Add: F240h DQ[10]=Error
Add: F240h DQ[10]=Error
Write ‘Finish Cache Read
FLASH MEMORY
Command’ @ Final Read
Add: F241h DQ[15]=INT
Read Controller Status
Add: F241h DQ[15]=INT
Read Controller Status
Wait for INT high State
Add: F220h DQ=000Ch
Add: F241h DQ=0000h
Wait for INT high State
Host reads data from
Host reads data from
DQ[10]=0?
DataRAM
DQ[10]=0?
Register
Yes
Register
Yes
DataRAM
* DBS, DFS is for DDP
END
6)
4)