sed1374 ETC-unknow, sed1374 Datasheet - Page 105
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sed1374
Manufacturer Part Number
sed1374
Description
Sed1374 Embedded Memory Color Lcd Controller
Manufacturer
ETC-unknow
Datasheet
1.SED1374.pdf
(420 pages)
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Epson Research and Development
Vancouver Design Center
2.1 Frame Rate Calculation
Programming Notes and Examples
Issue Date: 99/04/27
Register
[1E],[1F]
[1A]
[1B]
[1C]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
1111 1111 (FF)
0000 0000 (00)
0000 0011 (03)
0000 0000 (00)
0000 0000 (00)
0000 0000 (00)
0000 0000 (00)
0000 0000 (00)
0000 0000 (00)
0000 0000 (00)
0000 0000 (00)
0000 0000 (00)
Value (hex)
The system the SED1374 is being configured for dictates certain physical constraints such
as the width and height of the panel and the video system input clock.
The following are the formulae for determining the frame rate of a panel. The frame rate
for a single passive or TFT panel is calculated as follows:
for a dual passive panel the formula is:
where: PCLK
To achieve the desired frame rate the HNDP and VNDP values can be manipulated. The
example below is a generic routine to calculate HNDP and VNDP from a desired frame
rate.
Table 2-1: SED1374 Initialization Sequence (Continued)
Memory Address offset - not virtual setup so set to 0
Set the vertical size to the maximum value.
SetLUT control registers to 0 for this example.
GPIO control and status registers - set to “0”
Set the scratch pad bits to “0”.
We are not setting up SwivelView mode so set this register to “0”.
Line Byte Count is only required for SwivelView mode.
These registers are reserved and should not be written to.
HDP
HNDP
VDP
VNDP
FrameRate
FrameRate
= Pixel clock (in Hz)
= Horizontal Display Period (in pixels)
= Horizontal Non-Display Period (in pixels)
= Vertical Display Period (in lines)
= Vertical Non-Display Period (in lines)
=
=
------------------------------------------------------------------------------------------------- -
2
---------------------------------------------------------------------------------------- -
HDP
HDP
+
HNDP
+
Notes
HNDP
PCLK
PCLK
VDP
VDP
----------- -
2
+
+
VNDP
VNDP
Split Screen on page 30
Look-Up Table (LUT) on
page 14
See Also
X26A-G-002-02
SED1374
Page 9
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