sed1374 ETC-unknow, sed1374 Datasheet - Page 415

• Manufacturer Part Number: sed1374
• Description: Sed1374 Embedded Memory Color Lcd Controller
• Manufacturer: ETC-unknow

Epson Research and Development
Vancouver Design Center
4 8-Bit Processor to SED1374 Interface
4.1 Hardware Description
Interfacing to an 8-bit Processor
Issue Date: 99/05/04
Figure 4-1: Typical Implementation of an 8-bit Processor to the SED1374 Generic #2 Interface
Note:
When connecting the SED1374 RESET# pin, the system designer should be aware of all
conditions that may reset the SED1374 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
The interface between the SED1374 and an 8-bit processor requires minimal glue logic. A
decoder is used to generate the chip select for the SED1374 based on where the SED1374
is mapped into memory. Alternatively, if the processor supports a chip select module, it can
be programmed to generate a chip select for the SED1374 without the need of an address
decoder.
An inverter inverts A0 to generate the Byte High Enable signal for the SED1374. If the
8-bit host interface has an active high WAIT signal, it must be inverted as well.
In order to support an 8-bit microprocessor with a 16-bit peripheral, the low and high order
bytes of the data bus must be connected together. The following diagram shows a typical
implementation of an 8-bit processor to SED1374 interface.
Generic 8-bit Bus
BUSCLK
A[15:0]
WAIT#
D[7:0]
WE#
RD#
A0
System RESET
Decoder
IO V
DD
BUSCLK
RESET#
BHE# (WE1#)
RD/WR#
SED1374
WAIT#
DB[7:0]
DB[15:8]
RD#
BS#
AB[15:0]
CS#
WE0#
X26A-G-013-01
SED1374
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