sed1374 ETC-unknow, sed1374 Datasheet - Page 402

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sed1374

Manufacturer Part Number
sed1374
Description
Sed1374 Embedded Memory Color Lcd Controller
Manufacturer
ETC-unknow
Datasheet

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Page 12
4 CPU Module Description
4.1 Clock Signals
4.1.1 BUSCLK
4.1.2 CLKI
4.2 LCD Connectors
4.2.1 50-pin LCD Module Connector, J3
X00A-G-004-01
This section will describe the various parts of the CPU module that pertain to the
SED1374/75 LCD Controller.
Because the bus clock for the SED1374/75 does not need to be synchronous with the bus
interface control signals, a lot of flexibility is available in the choice for BUSCLK. In this
CPU module, BUSCLK is a divided by two version of the SDRAM clock signal,
DCLKOUT. Since DCLKOUT equals 73.728MHz, BUSCLK = 36.864MHz.
The pixel clock for the SED1374/75, CLKI, is also asynchronous with respect to the
interface control signals. This clock is selected based upon panel frame rates, power vs
performance budget, and maximum input frequencies. The maximum CLKI input is
25MHz if the internal CLKI/2 isn’t used, and if it is used the maximum input is 50MHz.
On the CPU module, CLKI’s default input is a divided by four version of DCLKOUT,
which gives a CLKI = 18.432MHZ. This frequency gives good performance for 320x240
resolution panels for both portrait and landscape modes. If power saving is desired, the
CLKI can be reduced by using the internal CLKI/2 and the various PCLK and MCLK
dividers for portrait mode.
A socket for an external oscillator is also provided if a different frequency is required. This
option is selected by positioning jumper JP8 in the 2 3 position and adding a standard 14-
DIP type oscillator in the socket U10.
The standard connector used on Toshiba’s CPU Modules to connect to the LCD module is
included in this CPU module. All twelve LCD data lines, FPDAT[11:0], from the
SED1374/75, as well as the five video control signals, FPFRAME, FPSHIFT, FPLINE,
DRDY, LCDPWR, are passed through this connector. Through this connector, the
SED1374/75 supports monochrome and color STN panels up to a resolution of 640x480 as
well as color TFT/D-TFT up to a resolution of 640x480. All touch panel signals from the
main board have also been routed through this connector.
SDU1374/75-TMPR3912/22U CPU Module
EPSON Research and Development
Vancouver Design Center
Issue Date: 98/12/23

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