sed1374 ETC-unknow, sed1374 Datasheet - Page 401
![no-image](/images/no-image-200.jpg)
sed1374
Manufacturer Part Number
sed1374
Description
Sed1374 Embedded Memory Color Lcd Controller
Manufacturer
ETC-unknow
Datasheet
1.SED1374.pdf
(420 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
sed137460B5
Manufacturer:
HIROSE
Quantity:
49 000
Company:
Part Number:
sed1374F0A
Manufacturer:
EPSON
Quantity:
650
Company:
Part Number:
sed1374FOA
Manufacturer:
NICHIA
Quantity:
12 000
Part Number:
sed1374FOA
Manufacturer:
EPSON/爱普生
Quantity:
20 000
- Current page: 401 of 420
- Download datasheet (2Mb)
EPSON Research and Development
Vancouver Design Center
3.2 Memory Mapping and Aliasing
3.3 SED1374/75 Configuration and Pin Mapping
SDU1374/75-TMPR3912/22U CPU Module
Issue Date: 98/12/23
Configuration
SED1374
CNF[2:0]
CNF3
BS#
Pin
= configuration for Toshiba TMPR3912/22U host bus interface
Note
The SED1374 requires an addressing space of 64K bytes while the SED1375 requires
128K. The on-chip display memory occupies the range 0 through 9FFFh. The registers
occupy the range FFE0h through FFFFh. The TMPR3912/22U demultiplexed address lines
A16 and above are ignored if the SED1374 is used, thus it is aliased 1024 times at 64K byte
intervals over the 64M byte PC Card slot #1 memory space. If the SED1375 is used, address
lines A17 and above are ignored; therefore the SED1375 is aliased 512 times at 128K byte
intervals. The TMPR3912/22U control signal CARDREG# is ignored; therefore the
SED1374 also takes up the entire PC Card slot #1 configuration space.
The SED1374/75 host bus interface is configured at power up by latching the state of the
CNF[3:0] pins. Pin BS# also plays a role in host bus interface configuration. One additional
configuration pin for the SED1374, CNF4, is also used to set the polarity of the LCDPWR
signal.
The table below shows the configuration pin connections to configure the SED1374/75 for
use with the TMPR3912/22U microprocessor.
When the SED1374/75 is configured for Generic #2 bus interface mode, the host interface
pins are mapped as in the table below.
Table 3-1: SED1374/75 Configuration for Generic #2 Bus Interface
If aliasing is undesirable, additional decoding circuitry must be added.
Table 3-2: SED1374/75 Generic #2 Interface Pin Mapping
Generic #2
Big Endian
1 (IO V
Value hard wired on this pin is used to configure:
DD
Pin Name
)
RD/WR#
WE1#
WE0#
BS#
RD#
Connect to IO V
Connect to IO V
111: Generic #1 or #2
Pin Function
BHE#
WE#
RD#
DD
DD
Little Endian
Generic #1
0 (V
SS
)
X00A-G-004-01
Page 11
Related parts for sed1374
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![BPW729-1230-27AB95L](/images/no-image3.png)
Part Number:
Description:
SE-BGG729, E-Tec lead free prototype socket drawing for BGG729 and BGG729 packages
Manufacturer:
ACTEL [Actel Corporation]
Datasheet:
![BPW128-0828-12CB95](/images/no-image3.png)
Part Number:
Description:
SE-CSG128-H, E-Tec lead free prototype socket drawing for CSG128 and CSG128 packages
Manufacturer:
ACTEL [Actel Corporation]
Datasheet:
![AA05B-005L-120D](/images/no-image3.png)
Part Number:
Description:
Manufacturer:
ETC-unknow
Datasheet:
![HM3-65787H-5](/images/no-image3.png)
Part Number:
Description:
Manufacturer:
ETC-unknow
Datasheet: