sed1374 ETC-unknow, sed1374 Datasheet - Page 323

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sed1374

Manufacturer Part Number
sed1374
Description
Sed1374 Embedded Memory Color Lcd Controller
Manufacturer
ETC-unknow
Datasheet

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Epson Research and Development
Vancouver Design Center
Interfacing to the PC Card Bus
Issue Date: 98/12/10
A[25:0]
REG#
A[25:0]
D[15:0]
D[15:0]
CE1#
CE2#
WAIT#
REG#
OE#
WAIT#
CE1#
CE2#
OE#
WE#
Transfer Start
During a read cycle, OE# (output enable) is driven low. A write cycle is specified by
driving OE# high and driving the write enable signal (WE#) low. The cycle can be
lengthened by driving WAIT# low for the time needed to complete the cycle.
Figure 2-1: and Figure 2-2: illustrate typical memory access cycles on the PC Card bus.
Transfer Start
Hi-Z
Hi-Z
Figure 2-2: PC Card Write Cycle
Figure 2-1: PC Card Read Cycle
ADDRESS VALID
ADDRESS VALID
DATA VALID
Transfer Complete
DATA VALID
Transfer Complete
X26A-G-009-02
Hi-Z
SED1374
Hi-Z
Page 9

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