sed1374 ETC-unknow, sed1374 Datasheet - Page 308

• Manufacturer Part Number: sed1374
• Description: Sed1374 Embedded Memory Color Lcd Controller
• Manufacturer: ETC-unknow

Page 12
SED1374
X26A-G-008-04
• The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in the bus inter-
refresh memory. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete. This signal is active low and may need to be
inverted if the host CPU wait state signal is active high.
face for Generic #2 mode. However, BS# is used to configure the SED1374 for
Generic #2 mode and should be tied high (connected to IO V
be tied high.
Interfacing to the NEC VR4102™ Microprocessor
Epson Research and Development
DD
). RD/WR# should also
Vancouver Design Center
Issue Date: 99/01/05