cx25870 Conexant Systems, Inc., cx25870 Datasheet - Page 124

• Manufacturer Part Number: cx25870
• Description: Video Encoder With Adaptive Flicker Filtering And Hdtv Output
• Manufacturer: Conexant Systems, Inc.

2.0 Internal Registers
2.4 Reading Registers
Table 2-5. Programming Detail For All Read/Write Registers (10 of 16)
2-18
HBURST_BEGIN[8]
HBURST_BEGIN
[7:0]
FM
GY_SYNC_DIS
H_ACTIVE[10:8]
H_ACTIVE[7:0]
H_BLANKI[9]
H_BLANKI[8]
H_BLANKI[7:0]
H_BLANKO[9:8]
H_BLANKO[7:0]
H_CLKI[10:8]
H_CLKI[7:0]
H_CLKO[11:8]
H_CLKO[7:0]
H_FRACT[7:0]
HALF_CLKO
HBURST_END[8]
HBURST_END[7:0]
HD_SYNC_EDGE
HDTV_EN
HSYNC_WIDTH
[7:0]
Bit/Register
Names
Bit 7–A2
Bit 4–2E
Bits [7:0]–88
Bit 7–28
Bits [7:0]–7A
Bits [6:4]–86 and
bits [7:0]–78
Bit 0–38, bit
3–8E, and
bits[7:0]–8C
Bits [7:6]–9A and
bits [7:0]–80
Bits [2:0]–8E and
bits [7:0]–8A
Bits [3:0]–86 and
bits [7:0]–76
Bit 3–3A
Bit2–38 and bits
[7:0]–7C
Bit 3–38 and bits
[7:0]–7E
Bit 2–2E
Bit Location
This bit must be enabled for a valid SECAM video output.
0 = QAM color encoding (NTSC/PAL). (DEFAULT)
1 = FM color encoding (SECAM).
This bit is only effective when OUT_MODE[1:0] = 11, HDTV_EN = 1, and RASTER_SEL is
nonzero.
0 = Enables trilevel sync on HDTV Green or Y output. (DEFAULT)
1 = Disables trilevel sync on HDTV Green or Y output.
Number of active input and output pixels.
Number of CLKI clock cycles between the digital HSYNC* leading edge and first active
pixel.
Number of CLKO clock cycles between leading edge of analog horizontal sync and active
video.
Number of CLKI clock cycles between consecutive leading edges of the digital HSYNC*
signal.
Number of CLKO clock cycles per analog line.
Fractional number of input clocks per line. No effect if 00.
0 = Normal operation. (DEFAULT)
1 = CLKO (clock output) frequency divided by 2 while being transmitted.
This register contains the number of CLKO clock cycles between the analog horizontal
sync falling edge and the 50% point of the first colorburst cycle.
This register contains the number of CLKO clock cycles minus 128 between the analog
horizontal sync falling edge and the 50% point of the last colorburst cycle. Make sure to
subtract 128 CLKO clock cycles from the calculated 50% point of the last colorburst
cycle value and load into this register.
nonzero.
0 = Trilevel sync edges transition time is equal to 4 input clocks. (DEFAULT)
1 = Trilevel sync edges transition time is equal to 2 input clocks.
Enable HDTV output mode, OUT_MODE[1:0] register bits must be set to 11 (VGA mode)
and EN_SCART must = 0.
0 = Enables VGA mode. DACs will output analog RGB with standard bilevel (-40 IRE)
analog syncs. (DEFAULT) See
1 = Enables HDTV output mode. DACs will output HDTV compatible RGB or component
video (Y/ P
inserted automatically if RASTER_SEL[1:0] = nonzero.
NOTE(S):
Analog horizontal sync width in number of CLKO clock cycles.
This bit is only effective when OUT_MODE[1:0] = 11, HDTV_EN = 1 and RASTER_SEL is
The EN_SCART bit must be 0 for HDTV Output Mode to be functional.
R
/ P
B
Conexant
) outputs. Trilevel syncs and vertical synchronizing/broad pulses will be
Flicker-Free Video Encoder with Ultrascale Technology
Section 1.3.45
Bit/Register Definition
for details.
CX25870/871
100381B