cx25870 Conexant Systems, Inc., cx25870 Datasheet - Page 39

• Manufacturer Part Number: cx25870
• Description: Video Encoder With Adaptive Flicker Filtering And Hdtv Output
• Manufacturer: Conexant Systems, Inc.

CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Table 1-8. Master Interface with a BLANK* Input to the CX25870/871
Table 1-9. Pseudo-Master Interface without a BLANK* Signal
100381B
MASTER
BLANK* SIGNAL
transmitted to the
CX25870/871 and
received as an input.
PSEUDO MASTER
BLANK* is NOT
included as part of
the interface.
Interfaced Used
Interfaced Used
0xBA) ORed with
0xBA) ORed with
SLAVER (Bit 5 of
SLAVER (Bit 5 of
Slave Pin
Slave Pin
0
1
• If the SLAVE pin is tied to GND, the state of the SLAVER bit dictates
• EN_BLANKO is high (=1), signifying the CX25870/871's BLANK* port
• EN_DOT = 0 telling the CX25870/871 to use its internal counters to
• EN_OUT = 1 ensures there is a clock output (CLKO) from the
• If the SLAVE pin is tied to GND, the state of the SLAVER bit dictates
• EN_BLANKO is low (= 0), signifying the CX25870/871's BLANK* port
• EN_DOT = 1 telling the CX25870/871 to use the BLANK* signal it is
• EN_OUT = 1 ensures there is a clock output (CLKO) from the
whether the CX25870/871 is the timing master or timing slave by
controlling the direction of the HSYNC* and VSYNC* ports. In other
words, SLAVER will determine whether the overall interface is master or
pseudo-master. The SLAVER bit allows the graphics controller vendor to
switch between master video timing and slave video timing through
software so long as the SLAVE pin (#51) is low.
is an output or that NO BLANK* signal is used as part of the system.
determine the active versus the blanking regions.
CX25870/871 and also enables HSYNC* and VSYNC* outputs.
whether the CX25870/871 is the timing master or timing slave by
controlling the direction of the HSYNC* and VSYNC* ports. In other
words, SLAVER determines whether the overall interface is master or
pseudo-master. The SLAVER bit allows the graphics controller vendor to
switch between master video timing and slave video timing through
software so long as SLAVE pin (#51) is low.
is an input.
receiving to determine where active video starts (rising edge of BLANK*)
and uses HACTIVE register to determine the start of the blanking region.
CX25870/871 and also enables HSYNC* and VSYNC* outputs.
EN_BLANKO (MSb
EN_BLANKO (MSb
of Register 0xC6)
of Register 0xC6)
Conexant
0
1
EN_DOT (Bit 6 of
EN_DOT (Bit 6 of
Register 0xC6)
Register 0xC6)
1
0
1.0 Functional Description
1.3 Device Description
EN_OUT (LSb of
EN_OUT (LSb of
Register 0xC4)
Register 0xC4)
1
1
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