cx25870 Conexant Systems, Inc., cx25870 Datasheet - Page 71

• Manufacturer Part Number: cx25870
• Description: Video Encoder With Adaptive Flicker Filtering And Hdtv Output
• Manufacturer: Conexant Systems, Inc.

CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
Figure 1-22. FIELD Pin Output Timing Diagram (PAL-B, D, G, H, I, N, Nc)
100381B
Composite
Composite
FIELD Pin
FIELD Pin
Output
Output
Output
Output
620
308
621
309
622
310
transmit a logical 1 during transmission of an EVEN field and logical 0 for the
period of an ODD field. To change the FIELD polarity, reprogram the FIELDI bit.
VSYNC*, then after a power-on, pin, or timing reset (setting of bit 7, register
0x6C), the encoder and the flicker filter portions of the device start at line 1, pixel
1 of their respective timing generation. For the CX25870/871, this means the
ODD field is always the first field conveyed after a power-on reset, pin reset, or
timing reset.
represents only the output field presently being generated by the on-chip DACs.
When the CX25870 receives progressive (i.e., noninterlaced) frames which have
no field associated with it, the CX25870’s input timing generator still keeps track
of frames received. As a result, after the entire second frame has been received,
the input and encoder sections become resynchronized. This re-synchronization is
done through an internal frame sync signal. This action, in turn, forces the
CX25870 to the beginning of the odd field and changes the FIELD pin back to its
odd state.
VSYNC*) receiving a power-on reset, pin reset, or timing reset (register 0x6C,
bit 7) causes the input timing generator to send the encoder the aforementioned
frame sync. This sets the encoder to the beginning of the odd field which is
denoted through the FIELD pin. The first digital HSYNC* and VSYNC*
combination then corresponds to the encoder’s EVEN output field. The second
digital HSYNC* and VSYNC* combination will again cause a frame sync and
the encoder will start sending the ODD field both from its DACs and FIELD pin.
This ODD–EVEN–ODD–EVEN … field sequence continues indefinitely.
623
By default, the internal FIELDI bit will be 0 which forces the CX25870 to
If the CX25870/871 is the timing master and sends out HSYNC* and
When the CX25870 receives an interlaced data format, its FIELD pin
If the CX25870/871 is the timing slave (i.e., it accepts HSYNC* and
311
624
312
625
VSYNC*
Start
313
of
1
RESET*
Conexant
Analog
FIELD 1
Analog
FIELD 2
314
2
315
3
316
4
317
5
318
6
319
7
1.0 Functional Description
320
*FIELDI Bit = 0
1.3 Device Description
23
336
24
337
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