cx25870 Conexant Systems, Inc., cx25870 Datasheet - Page 270

• Manufacturer Part Number: cx25870
• Description: Video Encoder With Adaptive Flicker Filtering And Hdtv Output
• Manufacturer: Conexant Systems, Inc.

Appendix E HDTV Output Mode
E.4 Interface Timing between the HDTV Source Device (Master) and CX25870/ CX25871(Timing Slave)
Table E-1. CX25870 Register Settings for Alternate 24-bit RGB Multiplexed In—HDTV YP
E-6
0xD6
0x2E
0x32
0x3C
0x3E
0x40
0xC4
0xC6
0xCE
0xA0
0x9E
0x9C
0xBA
WAIT state =
75 ms.
0x6C
(*) = If graphics controller is character based with 8 pixel clocks/character, PLL_INT should be modified to generate a 74.16000 MHz. CLKO and
CLKI frequency.
(**) = If graphics controller is character based with 8 pixel clocks/character, PLL_FRACT should be modified to generate a 74.16000 MHz. CLKO
and CLKI frequency.
CX25870
Register
Address
0C
C3
01
80
45
51
01
80
24
21
00
00
28
Yes
C6
1080i
0C
C2
01
80
45
51
01
80
24
21*
00**
00**
28
Yes
C6
720p
0C
C5
00
80
48
5B
01
80
24
8C
00
00
28
Yes
C6
480p
OUT_MODE [1:0] field set to 11=DAC Mode to turn on HDTV outputs.
Video[0-3] is HDTV Output Mode. HDTV_EN bit must be set as well.
Video[0] = HD R or PR, Video[1] = HD G or Y, Video[2] = HD B or PB
HDTV_EN set. RGB2YPRPB set. RASTER_SEL[1:0] field adjusted for each ATSC resolution.
HD_SYNC_EDGE set for 480p resolution only.
For RGB out, RGB2YPRPB bit must be 0 so this register will be 83 / 82 / and 85.
For EIA770.3 compliance, disable the trilevel sync on both the P
the RPR_SYNC_DIS(bit 5) and BPB_SYNC_DIS(bit 3) bits.
SETUP_HOLD_ADJ bit is bit 4.
CSC_SEL bit set for hi-frequency ATSC resolutions only.
MCOMPY stays the same for 480p/720p/1080i in, Y/PR/PB out. or RGB out.
MCOMPU must be changed for 480p and 720p/1080i in, Y/PR/PB out.
MCOMPU must be changed to 80hex for 480p/720p/1080i in, RGB out.
MCOMPV must be changed for 480p and 720p/1080i in, Y/PR/PB out.
MCOMPV must be changed to 80hex for 480p/720p/1080i in, RGB out.
State of EN_OUT varies according to interface used with master device. Hex value of 01 for
this register corresponds to Pseudo-Master without a BLANK* interface.
State of EN_BLANKO & EN_DOT varies
according to interface used with master device. Hex value of 80 for this register corresponds
to Pseudo-Master without a BLANK* interface.
IN_MODE[2:0] = 000 - defines input format as 24-bit RGB multiplexed.
Adjust this register as necessary to route Y/PR/PB out from the CX25870's 4 DACs
OUT_MUXD[1:0]= 00 =Video[0] = PR = R {Disabled from DACDISD=1}
OUT_MUXC[1:0]= 10 =Video[2] = PB = B
OUT_MUXB[1:0]= 01 =Video[1] = Y = G
OUT_MUXA[1:0]= 00 =Video[0] = PR = R
PLL_INT[5:0] = 21 for 720p @ 74.25 MHz
*PLL_INT[5:0] = 20 for 720p @ 74.16 MHz
PLL_FRACT[15:8] = 00 for 720p @ 74.25 MHz
**PLL_FRACT[15:8] = F5 for 720p @ 74.16 MHz
PLL_FRACT[7:0] = 00 for 720p @ 74.25 MHz
**PLL_FRACT[7:0] = C3 for 720p @ 74.16 MHz
SLAVER set. Interface is slave timing (pseudo-master or slave)
HSYNC*/VSYNC* sent to CX25870.
DACD disabled. PR/Y/PB transmitted from DACA/DACB/DACC
Ready encoder for timing reset operation. 75 ms = many factors of safety.
Set TIMING_RESET bit. Cleared automatically.
ATSC Resolution
Conexant
Explanation
B
P
R
Out and HDTV RGB Out
R
and P
Flicker-Free Video
B
outputs by setting
CX25870/871
100381B