cx25870 Conexant Systems, Inc., cx25870 Datasheet - Page 20

• Manufacturer Part Number: cx25870
• Description: Video Encoder With Adaptive Flicker Filtering And Hdtv Output
• Manufacturer: Conexant Systems, Inc.

1.0 Functional Description
1.1 Pin Descriptions
Table 1-1. Pin Assignments (3 of 3)
1-4
FIELD
VSYNC*
HSYNC*
P[23:21]
P[20:14]
P[13:0]
VSS
XTL_BFO
VDD
Pin Name
O
I/O
I/O
I
I
I
O
I/O
—
—
37
36
35
34-32
29-23
18-5
4, 21, 22,
31, 41
3
1, 2, 19,
20, 30,
60
Pin #
Field control output (TTL compatible). FIELD transitions after the rising edge of
CLK, two clock cycles following falling HSYNC*. It is a logical 0 during odd
fields and is a logical 1 during even fields. If unused, FIELD should be left as a
no connect.
Vertical sync input/output (TTL compatible). As an output (timing master
operation), VSYNC* is output following the rising edge of CLK. As an input
(timing slave operation), VSYNC* is clocked on the rising edge of CLK.
Horizontal sync input/output (TTL compatible). As an output (timing master
operation), HSYNC* is output following the rising edge of CLK. As an input
(timing slave operation), HSYNC* is clocked on the rising edge of CLK.
Pixel inputs. See
falling edge of CLK for multiplexed modes, and on the rising edge of CLK in
nonmultiplexed modes. A higher bit index corresponds to a greater bit
significance.
Digital ground for core logic. All AGND and VSS pins must be connected
together on the same PCB plane to prevent latchup.
Buffered crystal clock output. On power-up, the encoder will transmit a 0 to 3.3
V signal at a frequency equal to the frequency of the crystal found between the
XTALIN/XTALOUT ports. Normally the XTL_BFO output is at a rate of 13.500
MHz. If unused, XTL_BFO should be left as a no connect.
Digital power for core logic. All VAA and VDD pins must be connected together
on the same PCB plane to prevent latchup.
Conexant
Table
Flicker-Free Video Encoder with Ultrascale Technology
1-2. The input data is sampled on both the rising and
Description
CX25870/871
100381B