cx25870 Conexant Systems, Inc., cx25870 Datasheet - Page 57

• Manufacturer Part Number: cx25870
• Description: Video Encoder With Adaptive Flicker Filtering And Hdtv Output
• Manufacturer: Conexant Systems, Inc.

CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
1.3.21 Output Modes
1.3.22 Analog Horizontal Sync
100381B
The encoder can generate output video as Composite/Y-C(S-Video), YUV
component, VGA-style RGB, SCART, Component (YP
for HDTV. These outputs are selected by the OUT_MODE[1:0] register bits in
combination with the HDTV_EN and EN_SCART bits.
from input to output. Analog RGB is transmitted from a digital RGB input and
analog YCrCb is output from a digital YCrCb input.
analog RGB with a bilevel sync. In this mode, the R, G, and B input data is fed to
the DACs after the addition of the horizontal sync and, if the SETUP bit is one,
the setup pedestal is added. The output currents are scaled so that the DACs
output the proper 1 V full-scale (sync tip to peak white) levels for driving a CRT
monitor. The graphics controller must provide all the timing control (HSYNC and
VSYNC signals) for the monitor, which results in the encoder operating as a slave
in this case. Only the P[23:0], BLANK*, HSYNC*, and VSYNC* input pins and
the RGB analog output pins are active. The BLANK*, HSYNC*, and VSYNC*
pins are automatically enabled as inputs in this mode.
multiplexed to any DAC using the OUT_MUXA[1:0], OUT_MUXB[1:0],
OUT_MUXC[1:0], and OUT_MUXD[1:0] register bits. To do this, program the
2-bit value representing the desired type of output into the appropriate
OUT_MUXx[1:0] register. As an example, suppose a system requires composite
video (i.e., 00) to be output from DAC_A, chroma (10) on DAC_B, luma (01) on
DAC_C, and composite video (00) on DAC_D. This scheme could be
accomplished by programming register 0xC6 with 0001 1000 binary or 18 hex.
analog output. The allowable delay ranges from 0 (no delay) to 3 pixel clocks.
into a combined RLOAD of 37.5 " (doubly-terminated 75 " loads). Unused
outputs should be disabled by setting the corresponding DACDISx bit to
minimize the supply current or left as a no connect. Disabling unused DAC
outputs reduces cross chroma distortion and improves picture quality.
The HSYNC_WIDTH[7:0] register determines the duration of the horizontal
sync pulse. The beginning of the horizontal sync pulse corresponds to the reset of
the internal horizontal pixel counter. The horizontal line rate is determined by
H_CLKO[11:0]. The internal horizontal counter is reset to 1 at the beginning of
the horizontal sync and counts up to H_CLKO.
is programmable over a range of values by SYNC_AMP[7:0]. Incrementing the
sync amp by 1 increases the sync amplitude of the analog sync pulse by 30
millivolts.
While the encoder is in VGA style RGB, no color space conversion is possible
When outputting RGB with HDTV_EN = 0, the device outputs VGA/SVGA
Each of the four video signals generated by the OUT_MODE[1:0] field can be
The LUMADLY[1:0] register bits control the amount of delay for the Y_DLY
All digital-to-analog converters are designed to drive standard video levels
The sync rise and fall times are automatically controlled. The sync amplitude
Conexant
R
1.0 Functional Description
P
B
) for HDTV , or RGB
1.3 Device Description
1-41