cx25870 Conexant Systems, Inc., cx25870 Datasheet - Page 274

• Manufacturer Part Number: cx25870
• Description: Video Encoder With Adaptive Flicker Filtering And Hdtv Output
• Manufacturer: Conexant Systems, Inc.

Appendix E HDTV Output Mode
E.5 Automatic Trilevel Sync Generation
Table E-4. CX25870/CX25871 RASTER_SEL[1:0] Bit Functionality
E-10
NOTE(S):
(1)
(2)
(3)
RASTER_SEL
The CX25870/871 can also be programmed for EIA-770.3 1080i format compliance. To do so, set RASTER_SEL[1:0] = 11 and
set the BPB_SYNC_DIS and RPR_SYNC_DIS bits to 1 to disable the trilevel sync on the PB and PR signals.
The CX25870/871 can also be programmed for EIA-770.3 720p format compliance. To do so, set RASTER_SEL[1:0] = 10 and
set the BPB_SYNC_DIS and RPR_SYNC_DIS bits to 1 to disable the trilevel sync on the PB and PR signals.
To obtain any of these SMPTE specifications, visit Global Engineering Documents at: http://global.ihs.com/
[1]
1
1
0
0
RASTER_SEL
[0]
1
0
1
0
RASTER_SEL[1:0] bits and the resolutions/modes supported with each option.
relationships found in the various SMPTE specifications. All lines of the First and
Second Fields of an Interlaced System will contain the trilevel syncs. This
includes lines #1-5 and #564-567 of the 1080i format. Line 563 is an
extraordinary case and the reader should defer to the SMPTE 274M specification
for more details on this topic.
shown on the next page. Note that the CX25870/871 cannot transmit negative
voltages. As a result, the video output is offset by +350mV to accommodate the
negative sync levels listed in the governing specifications.
Trilevel sync periods dictated by
HSYNC*&VSYNC* input levels
The table below summarizes the different permutations of the
The inserted syncs will adhere to Figure 3 and the analog and digital timing
An illustration of the typical trilevel sync output from the CX25870/871is
1080i = SMPTE 274M
720p = SMPTE 296M
480p = SMPTE 293M
HDTV/ATSC Mode
Conexant
(2)
(1)
Flicker-Free Video Encoder with Ultrascale Technology
40 clock periods = 538.7ns
LOWSYNC period = width
LOWSYNC period (ns)
44 clock periods =
63 clock periods =
of VSYNC* input
592.6 ns
2.36 !s.
40 clock periods = 538.7ns
HIGHSYNC period = width
HIGHSYNC period (ns)
No HIGHSYNC period
44 clock periods =
of HSYNC* input
CX25870/871
592.6 ns
100381B