h8s-2138 Renesas Electronics Corporation., h8s-2138 Datasheet - Page 405

• Manufacturer Part Number: h8s-2138
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Bits 1 and 0—Clamp Waveform Mode Select 1 and 0 (CLMOD1, CLMOD0): These bits
select the signal source for the CLO signal (clamp waveform).
13.2.4
SEDGR is an 8-bit readable/writable register used to detect a rising edge on the timer connection
input pins and the occurrence of 2fH modification, and to determine the phase of the IVI and IHI
signals.
The upper 6 bits of SEDGR are initialized to 0 by a reset and in hardware standby mode. The
initial value of the lower 2 bits is undefined, since it depends on the pin states.
Bit 6
ISGENE
0
1
Bit
Initial value
Read/Write
Notes: 1. Only 0 can be written, to clear the flags.
Edge Sense Register (SEDGR)
2. The initial value is undefined since it depends on the pin states.
Bit 1
CLMOD1
0
1
0
1
R/(W) *
VEDG
7
0
1
Bit 0
CLMOD2
0
1
0
1
0
1
0
1
R/(W) *
HEDG
6
0
1
CEDG
R/(W) *
Description
The CL1 signal is selected
The CL2 signal is selected
The CL3 signal is selected
The CL4 signal is selected
5
0
1
HFEDG
R/(W) *
Section 13 Timer Connection [H8S/2138 Group]
4
0
1
Rev. 4.00 Jun 06, 2006 page 351 of 1004
VFEDG
R/(W) *
3
0
1
PREQF
R/(W) *
2
0
1
— *
IHI
REJ09B0301-0400
R
1
2
(Initial value)
— *
IVI
R
0
2