h8s-2138 Renesas Electronics Corporation., h8s-2138 Datasheet - Page 49

• Manufacturer Part Number: h8s-2138
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Table 13.9
Table 13.10 Meaning of VSYNCO Output in Each Mode......................................................... 368
Section 14 Watchdog Timer (WDT)
Table 14.1
Table 14.2
Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.1
Table 15.2
Table 15.3
Table 15.4
Table 15.5
Table 15.6
Table 15.7
Table 15.8
Table 15.9
Table 15.10 Serial Transfer Formats (Asynchronous Mode) ..................................................... 420
Table 15.11 Receive Errors and Conditions for Occurrence...................................................... 429
Table 15.12 Bit IrCKS2 to IrCKS0 Settings .............................................................................. 449
Table 15.13 SCI Interrupt Sources ............................................................................................. 450
Table 15.14 State of SSR Status Flags and Transfer of Receive Data ...................................... 451
Section 16 I
Table 16.1
Table 16.2
Table 16.3
Table 16.4
Table 16.5
Table 16.6
Table 16.7
Table 16.8
Section 17 Host Interface [H8S/2138 Group]
Table 17.1
Table 17.2
Table 17.3
Table 17.4
Table 17.5
Table 17.6
Table 17.7
Meaning of HSYNCO Output in Each Mode......................................................... 367
WDT Pin ................................................................................................................ 374
WDT Registers....................................................................................................... 374
SCI Pins.................................................................................................................. 390
SCI Registers.......................................................................................................... 391
BRR Settings for Various Bit Rates (Asynchronous Mode) .................................. 406
BRR Settings for Various Bit Rates (Synchronous Mode) .................................... 409
Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................ 411
Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. 412
Maximum Bit Rate with External Clock Input (Synchronous Mode) .................... 413
SMR Settings and Serial Transfer Format Selection.............................................. 418
SMR and SCR Settings and SCI Clock Source Selection ...................................... 418
I
Register Configuration ........................................................................................... 459
Flags and Transfer States ....................................................................................... 474
I
Examples of Operation Using the DTC.................................................................. 499
I
Permissible SCL Rise Time (t
I
Host Interface Registers ......................................................................................... 526
Set/Clear Timing for STR1 Flags........................................................................... 532
Set/Clear Timing for STR2 Flags........................................................................... 535
Host Interface Channel Selection and Pin Operation ............................................. 536
Host Interface Operation ........................................................................................ 537
GA20 (P81) Set/Clear Timing................................................................................ 538
2
Host Interface Input/Output Pins........................................................................... 525
2
2
2
2
C Bus Interface [H8S/2138 Group Option]
C Bus Interface Pins............................................................................................. 458
C Bus Data Format Symbols................................................................................ 487
C Bus Timing (SCL and SDA Output) ................................................................ 507
C Bus Timing (with Maximum Influence of t
Sr
) Values ................................................................. 508
Rev. 4.00 Jun 06, 2006 page xlix of liv
Sr
/t
Sf
)............................................... 509