h8s-2138 Renesas Electronics Corporation., h8s-2138 Datasheet - Page 468

• Manufacturer Part Number: h8s-2138
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 15 Serial Communication Interface (SCI, IrDA)
Bit 2—Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does not
affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/E bit in
SMR.
Bit 2
SINV
0
1
Bit 1—Reserved: This bit cannot be modified and is always read as 1.
Bit 0—Serial Communication Interface Mode Select (SMIF): Reserved bit. 1 should not be
written in this bit.
Bit 0
SMIF
0
1
15.2.10 Module Stop Control Register (MSTPCR)
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When bit MSTP7, MSTP6, or MSTP5 is set to 1, SCI0, SCI1, or SCI2 operation, respectively,
stops at the end of the bus cycle and a transition is made to module stop mode. For details, see
section 24.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Rev. 4.00 Jun 06, 2006 page 414 of 1004
REJ09B0301-0400
Bit
Initial value
Read/Write
Description
TDR contents are transmitted without modification
Receive data is stored in RDR without modification
TDR contents are inverted before being transmitted
Receive data is stored in RDR in inverted form
Description
Normal SCI mode
Reserved mode
MSTP15
R/W
7
0
MSTP14
R/W
6
0
MSTP13
R/W
5
1
MSTPCRH
MSTP12
R/W
4
1
MSTP11
R/W
3
1
MSTP10
R/W
2
1
MSTP9
R/W
1
1
MSTP8
R/W
0
1
MSTP7
R/W
7
1
MSTP6
R/W
6
1
MSTP5
R/W
5
1
MSTPCRL
MSTP4
R/W
4
1
MSTP3
R/W
3
1
MSTP2
R/W
2
1
(Initial value)
(Initial value)
MSTP1
R/W
1
1
MSTP0
R/W
0
1