h8s-2138 Renesas Electronics Corporation., h8s-2138 Datasheet - Page 565

• Manufacturer Part Number: h8s-2138
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

SCL
Internal clock
SDA
BBSY bit
Clearing of the MST bit after completion of master transmission/reception, or other
modifications of IIC control bits to change the transmit/receive operating mode or settings,
must be carried out during interval (a) in figure 16.18 (after confirming that the BBSY bit has
been cleared to 0 in the ICCR register).
Notes on Start Condition Issuance for Retransmission
Figure 16.19 shows the timing of start condition issuance for retransmission, and the timing for
subsequently writing data to ICDR, together with the corresponding flowchart. After
retransmission start condition issuance is done and determined the start condition, write the
transmit data to ICDR, as shown below.
Figure 16.18 Points for Attention Concerning Reading of Master Receive Data
Master receive mode
Bit 0
8
A
9
Execution of stop
condition issuance
instruction
(0 written to BBSY
and SCP)
ICDR reading
prohibited
Section 16 I
Confirmation of stop
condition generation
(0 read from BBSY)
Rev. 4.00 Jun 06, 2006 page 511 of 1004
Stop condition
2
C Bus Interface [H8S/2138 Group Option]
(a)
Start condition
issuance
REJ09B0301-0400
Start condition