KSZ8851-16MLLJ_10 MICREL [Micrel Semiconductor], KSZ8851-16MLLJ_10 Datasheet - Page 24

• Manufacturer Part Number: KSZ8851-16MLLJ_10
• Description: Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel, Inc.
KSZ8851-16MLLJ
The KSZ8851-16MLLJ issues a flow control frame (Xoff, or transmitter off), containing the maximum pause time defined in
IEEE standard 802.3x. Once the resource is freed up, the KSZ8851-16MLLJ sends out the another flow control frame
(Xon, or transmitter on) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis
feature is provided to prevent the flow control mechanism from being constantly activated and deactivated.
Half-Duplex Backpressure
A half-duplex backpressure option (non-IEEE 802.3 standards) is also provided. The activation and deactivation
conditions are the same as in full-duplex mode. If backpressure is required, the KSZ8851-16MLLJ sends preambles to
defer the other stations' transmission (carrier sense deference).
To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KSZ8851-16MLLJ
discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other
stations from sending out packets thus keeping other stations in a carrier sense deferred state. If the port has packets to
send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets are
transmitted instead. If there are no additional packets to send, carrier sense type backpressure is reactivated again until
chip resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is
generated immediately, thus reducing the chance of further collision and carrier sense is maintained to prevent packet
reception.
Address Filtering Function
The KSZ8851-16MLLJ supports 11 different address filtering schemes as shown in the following Table 3. The Ethernet
destination address (DA) field inside the packet is the first 6-byte field which uses to compare with either the host MAC
address registers (0x10 – 0x15) or the MAC address hash table registers (0xA0 – 0xA7) for address filtering operation.
The first bit (bit 40) of the destination address (DA) in the Ethernet packet decides whether this is a physical address if bit
40 is “0” or a multicast address if bit 40 is “1”.
March 2010
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M9999-030210-1.0